dlhdl.ProcessorConfig Class

Namespace: dlhdl

Configure custom deep learning processor

Description

Use the dlhdl.ProcessorConfig class to configure a custom processor, which is then passed on to the dlhdl.buildProcessor class to generate a custom deep learning processor.

Creation

The dlhdl.ProcessorConfig class creates a custom processor configuration object that you can use to specify the processor parameters. The processor parameters are then used by the dlhdl.buildProcessor class to build and generate code for your custom deep learning processor.

dlhdl.ProcessorConfig(Name,Value) creates a custom processor configuration object, with additional options specified by one or more name-value arguments.

Properties

System Level Properties

ReferenceDesign — Reference design name

'AXI-Stream DDR Memory Access : 3-AXIM' (default) | 'Deep Learning with Preprocessing Interface' | 'AXI-Stream BRAM Memory Access : 3-AXIM' | character vector

Reference design name, specified as a character vector

Example: 'AXI-Stream DDR memory Access : 3-AXIM'

SynthesisTool — Synthesis tool name

'Xilinx Vivado' (default) | 'Altera Quartus II' | 'Xilinx ISE' | character vector

Synthesis tool name, specified as a character vector.

Example: Xilinx Vivado

SynthesisToolChipFamily — Synthesis tool chip family name

'Zynq Ultrascale+ (default) | 'Artix7' | 'Kintex7' | 'Kintex Ultrascale+' | 'Spartan7' | 'Virtex7' | 'Virtex Ultrascale+' | 'Zynq' | 'Arria 10' | 'Arria V GZ' | 'Cyclone 10 GX' | 'Stratix 10' | 'Stratix V' | character vector

Specify the target device chip family name as a character vector

Example: 'Zynq'

SynthesisToolDeviceName — Synthesis tool device name

'' (default) | character vector

Synthesis tool device name specified as a character vector. When you specify the TargetPlatform, this field is populated with the default value for that target platform.

SynthesisToolPackageName — Synthesis tool package name

'' (default) | character vector

Synthesis tool package name specified as a character vector. When you specify the TargetPlatform, this field is populated with the default value for that target platform.

SynthesisToolSpeedValue — Synthesis tool speed value

'' (default) | character vector

Synthesis tool speed value specified as a character vector. When you specify the TargetPlatform, this field is populated with the default value for that target platform.

Example: -2

TargetFrequency — Target frequency in MHz

200 (default) | integer

Specify the target board frequency in MHz.

Example: 220

TargetPlatform — Name of the target board

'Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit' (default) | 'Generic Deep Learning Processor' | 'Intel Arria 10 SoC development kit' | 'Xilinx Zynq ZC706 evaluation kit' | 'Xilinx Kintex-Ultrascale KCU105 evaluation board' | character vector

Specify the name of the target board as a character vector.

Example: 'Xilinx Zynq ZC706 evaluation kit'

Bitstream — Name of the bitstream

'arria10soc_single' | 'arria10soc_int8' | 'arria10soc_lstm_single' | 'zc706_single' | 'zc706_int8' | 'zcu102_single' | 'zcu102_int8' | 'zcu102_lstm_single' | 'zc706_lstm_single'

Specify the name of the bitstream whose processor configuration must be retrieved as a character vector.

Example: 'Bitstream','zcu102_single'

Top Level Properties

RunTimeControl — Deep learning processor IP core mode setting

'register' (default) | 'port' | character vector

Specify whether the runtime input signals to the deep learning processor IP core are implemented as registers or ports.

Example: 'register

RunTimeStatus — Feedback signals from deep learning processor IP core control

'register' (default) | 'port'

Specify whether the runtime output signals from the deep learning processor IP core are implemented as registers or ports.

Example: 'register'

InputStreamControl — Deep learning processor IP core input interface control

'register' (default) | 'port' | character vector

Specify the deep learning processor IP core input interface option as a character vector

Example: 'register'

OutputStreamControl — Deep learning processor IP core output interface control

'register' (default) | 'port' | character vector

Specify the deep learning processor IP core output interface option as a character vector

Example: 'port'

SetupControl — Deep learning processor IP core user interface control

'register' (default) | 'port' | character vector

Specify the deep learning processor IP core user interface option as a character vector

Example: 'port'

ProcessorDataType — Deep learning processor IP core module data type

'single (default) | 'int8' | character vector

Specify the deep learning processor IP core module data type as a character vector.

Example: 'single'

UseVendorLibrary — Option to use vendor-specific floating point libraries

'on' (default) | 'off'

Option to use vendor-specific floating point libraries, specified as a character vector. When the option is set to 'on' Deep Learning HDL Toolbox™ uses a mixture of native floating-point (NFP) and vendor-specific floating point IPs to generate HDL code. When the option is set to 'off' Deep Learning HDL Toolbox uses native floating-point (NFP) libraries to generate HDL code.

When you set ProcessorDataType to int8, you must set UseVendorLibrary to 'off'. The option is set to on when ProcessorDataType is single.

Example: UseVendorLibrary = 'on'

LayerNormalizationBlock — Option to enable or disable layer normalization layer generation

"off" (default) | "on"

Option to enable or disable layer normalization layer generation, specified as a string or character vector. When you enable this layer, Deep Learning HDL Toolbox enables generation of the fc and custom processing modules.

Example: LayerNormalizationBlock = "on"

Processing Module conv Properties

ModuleGeneration — Enable or disable convolution module generation as a part of the deep learning processor configuration

'on' (default) | 'off' | character vector

Use this parameter to control generation of the convolution module as a part of the deep learning processor configuration.

LRNBlockGeneration — Enable or disable local response normalization (LRN) block generation as a part of the convolution module of the deep learning processor configuration

'off' (default) | 'on' | character vector

Use this parameter to control generation of the LRN block as a part of the convolution module of the deep learning processor configuration.

SegmentationBlockGeneration — Enable or disable segmentation block generation as a part of the convolution module of the deep learning processor configuration

'on' (default) | 'off' | character vector

Use this parameter to control generation of the segmentation block as a part of the convolution module of the deep learning processor configuration.

GELUBlockGeneration — Option to enable or disable Gaussian error linear unit (GELU) block

'off' (default) | 'on' | character vector

Option to enable or disable Gaussian error linear unit (GELU) block, specified as a character vector.

ConvThreadNumber — Number of parallel convolution processor kernel threads

16 (default) | 4 | 9 | 16 | 25 | 36 | 64 | 256 | unsigned integer

This parameter is the number of parallel 3-by-3 convolution kernel threads that are a part of the conv module within the dlhdl.ProcessorConfig object. To set the ConvThreadNumber to 256 the ProcessorDataType parameter must be set to int8 data type.

InputMemorySize — Cache block RAM (BRAM) sizes

[227 227 3] (default) | 3D positive integer array

This parameter is a 3D matrix representing size of the input buffer RAM on the FPGA for the conv module.

OutputMemorySize — Cache block RAM (BRAM) sizes

[227 227 3] (default) | 3D positive integer array

This parameter is a 3D matrix representing output image size limited by the conv module BRAM size within the dlhdl.ProcessorConfig object.

FeatureSizeLimit — Maximum input and output feature size

2048 (default) | positive integer

This parameter is a positive integer representing the maximum input and output feature size as a part of the conv module within the dlhdl.ProcessorConfig object.

Processing Module fc Properties

ModuleGeneration — Enable or disable fully connected module generation as a part of the deep learning processor configuration

'on' (default) | 'off' | character vector

Use this parameter to control generation of the fully connected module as a part of the deep learning processor configuration.

SoftmaxBlockGeneration — Enable or disable Softmax block generation as a part of the fully connected module of the deep learning processor configuration

'off' (default) | 'on' | character vector

Use this parameter to control generation of the Softmax block as a part of the fully connected module of the deep learning processor configuration. When you set this property to off, the Softmax layer is still implemented in software.

GELUBlockGeneration — Option to enable or disable Gaussian error linear unit (GELU) block

'off (default) | 'on' | character vector

Option to enable or disable Gaussian error linear unit (GELU) block, specified as a character vector.

FCThreadNumber — Number of parallel fully connected (fc) MAC threads

4 (default) | 4 | 8 | 16 | 32 | 64 | unsigned integer

This parameter is the number of parallel fc MAC threads that are a part of the fc module within the dlhdl.ProcessorConfig object. To set the FCThreadNumber to 32 or 64 the ProcessorDataType parameter must be set to int8 data type.

InputMemorySize — Cache block RAM (BRAM) sizes

25088 (default) | unsigned integer

This parameter is a 3D matrix representing size of the input buffer RAM on the FPGA for the fc module.

OutputMemorySize — Cache block RAM (BRAM) sizes

4096 (default) | unsigned integer

This parameter is an unsigned integer representing cache BRAM size limited by the fc module BRAM size within the dlhdl.ProcessorConfig object.

Processing Module custom Properties

ModuleGeneration — Enable or disable custom module generation as a part of the deep learning processor configuration

'on' (default) | 'off' | character vector

Use this parameter to control generation of the adder module as a part of the deep learning processor configuration.

Addition — Enable or disable addition layer generation as a part of the custom module of the deep learning processor configuration

'on' (default) | 'off' | character vector

Use this parameter to control generation of the addition layer as a part of the custom module of the deep learning processor configuration.

MishLayer — Enable or disable mish layer generation as a part of the custom module of the deep learning processor configuration

'off' (default) | 'on | character vector

Use this parameter to control generation of the mish layer as a part of the custom module of the deep learning processor configuration.

Multiplication — Enable or disable multiplication layer generation as a part of the custom module of the deep learning processor configuration

'on' (default) | 'off' | character vector

Use this parameter to control generation of the multiplication layer as a part of the custom module of the deep learning processor configuration.

Resize2D — Enable or disable resize2d layer generation as a part of the custom module of the deep learning processor configuration

'off' (default) | 'on' | character vector

Use this parameter to control generation of the resize2d layer as a part of the custom module of the deep learning processor configuration.

Sigmoid — Enable or disable sigmoid layer generation as a part of the custom module of the deep learning processor configuration

'off' (default) | 'on' | character vector

Use this parameter to control generation of the sigmoid layer as a part of the custom module of the deep learning processor configuration.

SwishLayer — Enable or disable swish layer generation as a part of the custom module of the deep learning processor configuration

'off' (default) | 'on' | character vector

Use this parameter to control generation of the swish layer as a part of the custom module of the deep learning processor configuration.

TanhLayer — Enable or disable tanh layer generation as a part of the custom module of the deep learning processor configuration

'off' (default) | 'on' | character vector

Use this parameter to control generation of the tanh layer as a part of the custom module of the deep learning processor configuration.

InputMemorySize — Cache block RAM (BRAM) sizes

40 (default) | unsigned integer

This parameter is an unsigned integer representing cache BRAM size limited by the adder module BRAM size within the dlhdl.ProcessorConfig object.

OutputMemorySize — Cache block RAM (BRAM) sizes

120 (default) | unsigned integer

This parameter is an unsigned integer representing cache BRAM size limited by the adder module BRAM size within the dlhdl.ProcessorConfig object.

Methods

Public Methods

buildCalibrationBitstream	Generate calibration bitstream to obtain double data rate (DDR) RAM response time
deployCalibrationBitstream	Deploy calibration bitstream and generate calibration data file
getModuleProperty	Use the getModuleProperty method to get values of module properties within the dlhdl.ProcessorConfig object
setModuleProperty	Use the setModuleProperty method to set properties of modules within the dlhdl.ProcessorConfig object
estimatePerformance	Retrieve layer-level latencies and performance by using estimatePerformance method
estimateResources	Return estimated resources used by custom bitstream configuration
optimizeConfigurationForNetwork	Update network-specific deep learning processor configuration with optimized deep learning processor configuration
openCustomLayerModel	Open a generated custom layer verification model to verify your custom layers
registerCustomLayer	Register the custom layer definition and Simulink model representation of the custom layer
verifyCustomLayerModel	Verify the functionality and accuracy of the custom layer by using the generated custom layer verification model

Examples

Create a ProcessorConfig Object

Create a custom processor configuration. Save the ProcessorConfig object to hPC.

hPC = dlhdl.ProcessorConfig

The result is:

hPC = 

                    Processing Module "conv"
                            ModuleGeneration: 'on'
                          LRNBlockGeneration: 'off'
                 SegmentationBlockGeneration: 'on'
                         GELUBlockGeneration: 'off'
                            ConvThreadNumber: 16
                             InputMemorySize: [227 227 3]
                            OutputMemorySize: [227 227 3]
                            FeatureSizeLimit: 2048

                      Processing Module "fc"
                            ModuleGeneration: 'on'
                      SoftmaxBlockGeneration: 'off'
                         GELUBlockGeneration: 'off'
                              FCThreadNumber: 4
                             InputMemorySize: 25088
                            OutputMemorySize: 4096

                  Processing Module "custom"
                            ModuleGeneration: 'on'
                                    Addition: 'on'
                                   MishLayer: 'off'
                              Multiplication: 'on'
                                    Resize2D: 'off'
                                     Sigmoid: 'off'
                                  SwishLayer: 'off'
                                   TanhLayer: 'off'
                             InputMemorySize: 40
                            OutputMemorySize: 120

              Processor Top Level Properties
                              RunTimeControl: 'register'
                               RunTimeStatus: 'register'
                          InputStreamControl: 'register'
                         OutputStreamControl: 'register'
                                SetupControl: 'register'
                           ProcessorDataType: 'single'
                            UseVendorLibrary: 'on'
                     LayerNormalizationBlock: 'off'

                     System Level Properties
                              TargetPlatform: 'Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit'
                             TargetFrequency: 200
                               SynthesisTool: 'Xilinx Vivado'
                             ReferenceDesign: 'AXI-Stream DDR Memory Access : 3-AXIM'
                     SynthesisToolChipFamily: 'Zynq UltraScale+'
                     SynthesisToolDeviceName: 'xczu9eg-ffvb1156-2-e'
                    SynthesisToolPackageName: ''
                     SynthesisToolSpeedValue: ''

Modify Properties of ProcessorConfig Object

Modify the TargetPlatform, SynthesisTool, and TargetFrequency properties of hPC.

hPC.TargetPlatform = 'Xilinx Zynq ZC706 evaluation kit';
>> hPC.SynthesisTool = 'Xilinx Vivado';
>> hPC.TargetFrequency = 180;
hPC

The result is:

hPC = 

                    Processing Module "conv"
                            ModuleGeneration: 'on'
                          LRNBlockGeneration: 'off'
                 SegmentationBlockGeneration: 'on'
                         GELUBlockGeneration: 'off'
                            ConvThreadNumber: 16
                             InputMemorySize: [227 227 3]
                            OutputMemorySize: [227 227 3]
                            FeatureSizeLimit: 2048

                      Processing Module "fc"
                            ModuleGeneration: 'on'
                      SoftmaxBlockGeneration: 'off'
                         GELUBlockGeneration: 'off'
                              FCThreadNumber: 4
                             InputMemorySize: 25088
                            OutputMemorySize: 4096

                  Processing Module "custom"
                            ModuleGeneration: 'on'
                                    Addition: 'on'
                                   MishLayer: 'off'
                              Multiplication: 'on'
                                    Resize2D: 'off'
                                     Sigmoid: 'off'
                                  SwishLayer: 'off'
                                   TanhLayer: 'off'
                             InputMemorySize: 40
                            OutputMemorySize: 120

              Processor Top Level Properties
                              RunTimeControl: 'register'
                               RunTimeStatus: 'register'
                          InputStreamControl: 'register'
                         OutputStreamControl: 'register'
                                SetupControl: 'register'
                           ProcessorDataType: 'single'
                            UseVendorLibrary: 'on'
                     LayerNormalizationBlock: 'off'

                     System Level Properties
                              TargetPlatform: 'Xilinx Zynq ZC706 evaluation kit'
                             TargetFrequency: 180
                               SynthesisTool: 'Xilinx Vivado'
                             ReferenceDesign: 'AXI-Stream DDR Memory Access : 3-AXIM'
                     SynthesisToolChipFamily: 'Zynq'
                     SynthesisToolDeviceName: 'xc7z045'
                    SynthesisToolPackageName: 'ffg900'
                     SynthesisToolSpeedValue: '-2'

Retrieve ProcessorConfig Object for zcu102_single Bitstream

Retrieve the ProcessorConfig object for the zcu102_single bitstream and store the object in hPC.

hPC = dlhdl.ProcessorConfig('Bitstream','zcu102_single')

The result is:

hPC = 

                    Processing Module "conv"
                            ModuleGeneration: 'on'
                          LRNBlockGeneration: 'off'
                 SegmentationBlockGeneration: 'on'
                         GELUBlockGeneration: 'off'
                            ConvThreadNumber: 16
                             InputMemorySize: [227 227 3]
                            OutputMemorySize: [227 227 3]
                            FeatureSizeLimit: 2048

                      Processing Module "fc"
                            ModuleGeneration: 'on'
                      SoftmaxBlockGeneration: 'off'
                         GELUBlockGeneration: 'off'
                              FCThreadNumber: 4
                             InputMemorySize: 25088
                            OutputMemorySize: 4096

                  Processing Module "custom"
                            ModuleGeneration: 'on'
                                    Addition: 'on'
                                   MishLayer: 'off'
                              Multiplication: 'on'
                                    Resize2D: 'on'
                                     Sigmoid: 'off'
                                  SwishLayer: 'off'
                                   TanhLayer: 'off'
                             InputMemorySize: 40
                            OutputMemorySize: 120

              Processor Top Level Properties
                              RunTimeControl: 'register'
                               RunTimeStatus: 'register'
                          InputStreamControl: 'register'
                         OutputStreamControl: 'register'
                                SetupControl: 'register'
                           ProcessorDataType: 'single'
                            UseVendorLibrary: 'on'
                     LayerNormalizationBlock: 'off'

                     System Level Properties
                              TargetPlatform: 'Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit'
                             TargetFrequency: 220
                               SynthesisTool: 'Xilinx Vivado'
                             ReferenceDesign: 'AXI-Stream DDR Memory Access : 3-AXIM'
                     SynthesisToolChipFamily: 'Zynq UltraScale+'
                     SynthesisToolDeviceName: 'xczu9eg-ffvb1156-2-e'
                    SynthesisToolPackageName: ''
                     SynthesisToolSpeedValue: ''

Set the ProcessorConfig Object Module Data Type to int8

Create a custom processor configuration. Save the ProcessorConfig object to hPC.

hPC = dlhdl.ProcessorConfig

Modify the ProcessorDataType to int8. When you set ProcessorDataType to int8, you must set UseVendorLibrary to 'off'.

hPC.ProcessorDataType = 'int8'
hPC.UseVendorLibrary = 'off'

The result is:

hPC = 

                    Processing Module "conv"
                            ModuleGeneration: 'on'
                          LRNBlockGeneration: 'off'
                 SegmentationBlockGeneration: 'on'
                         GELUBlockGeneration: 'off'
                            ConvThreadNumber: 16
                             InputMemorySize: [227 227 3]
                            OutputMemorySize: [227 227 3]
                            FeatureSizeLimit: 2048

                      Processing Module "fc"
                            ModuleGeneration: 'on'
                      SoftmaxBlockGeneration: 'off'
                         GELUBlockGeneration: 'off'
                              FCThreadNumber: 4
                             InputMemorySize: 25088
                            OutputMemorySize: 4096

                  Processing Module "custom"
                            ModuleGeneration: 'on'
                                    Addition: 'on'
                                   MishLayer: 'off'
                              Multiplication: 'on'
                                    Resize2D: 'off'
                                     Sigmoid: 'off'
                                  SwishLayer: 'off'
                                   TanhLayer: 'off'
                             InputMemorySize: 40
                            OutputMemorySize: 120

              Processor Top Level Properties
                              RunTimeControl: 'register'
                               RunTimeStatus: 'register'
                          InputStreamControl: 'register'
                         OutputStreamControl: 'register'
                                SetupControl: 'register'
                           ProcessorDataType: 'int8'
                            UseVendorLibrary: 'off'
                     LayerNormalizationBlock: 'off'

                     System Level Properties
                              TargetPlatform: 'Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit'
                             TargetFrequency: 200
                               SynthesisTool: 'Xilinx Vivado'
                             ReferenceDesign: 'AXI-Stream DDR Memory Access : 3-AXIM'
                     SynthesisToolChipFamily: 'Zynq UltraScale+'
                     SynthesisToolDeviceName: 'xczu9eg-ffvb1156-2-e'
                    SynthesisToolPackageName: ''
                     SynthesisToolSpeedValue: ''

Version History

Introduced in R2020b