Using HDL Optimized CRC Library Blocks

This example uses:

This example shows how to use the HDL Optimized CRC Generator and CRC Detector library blocks and then configure these blocks to meet the IEEE® 802.11 standard [ 1 ].

Introduction

The model shows how to use HDL Optimized CRC Generator and Detector library blocks for simulation and HDL Code generation. The 802.11 standard is used as the application. To learn more about HDL support for HDL Optimized CRC blocks, refer to the General CRC Generator HDL Optimized block. To learn more about the algorithm used in the blocks, refer to the paper in [ 2 ].

To open this example model, run the following commands:

modelname = 'commcrchdl';
open_system(modelname);

In this model, the top-level subsystem CRC Subsystem contains the HDL Optimized CRC Generator and Detector blocks. This subsystem also has an AddNoise subsystem that you can choose to add noise to the generated CRC checksum. To open this subsystem, run the following commands:

systemname = [modelname '/CRC Subsystem'];
open_system(systemname);

Parameter Settings

Polynomial

CRC-CCITT is used in the IEEE® 802.11 standard to protect the SIGNAL, SERVICE and LENGTH fields. The row vector [1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1] represents the polynomial:

Initial state

The HDL optimized CRC Generator block in the demo uses the Direct Method, that means, it feeds the message into the most significant bit (MSB) of the checksum shift register and processes the message without padding zeros. The diagram of the IEEE 802.11 CRC implementation is illustrated in Figure 15-2 of the 802.11 standard. The Initial state is set as 1.

Final XOR value

The Final XOR value is set as 0xFFFF to implement the one's complement of the CRC Checksum.

Input Signals

The test vector in this model uses the example DBPSK signal specified in the 802.11 standard. The test data padded with crc_len zeros is processed at 16 bits/sample in streaming mode. Variable dataIn_width, which is the port width of the CRC Generator input port dataIn, defines the data processing speed. mlen defines the period in the controls signals startIn, endIn, and validIn. dlen defines the pulse width of the validIn signal. The input signals are configured in the InitFcn callback function in the Model Properties dialog box.

 %DBPSK data
 data = [0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0];
 crc_len = 16;
 % pad crc_len zero
 msg = [data zeros(1,crc_len)];
 dataIn_width = 16;
 mlen = length(msg)/dataIn_width;
 dlen = length(data)/dataIn_width;

To meet your design requirements, You can alter the dataIn_width to 8,4, 2, or 1 bit(s) in this example. For example, if you are processing data with length 56, aside from padding 8 bit zeros and using dataIn_width 16, you can choose dataIn_width to be 8 to ensure mlen and dlen are all integer numbers.

Output Signals

Run the model using the following command:

sim(modelname);

Several of the key signals have been logged into the workspace. These signals can be viewed in a Logic Analyzer window. The function commcrchdl_plot shows how to set the Logic Analyzer display. For further information on the Logic Analyzer System object™, refer to the dsp.LogicAnalyzer.

h = commcrchdl_plot(dataIn,startIn,endIn,validIn,...
                dataOut_gen,startOut_gen,endOut_gen,validOut_gen,...
                dataIn_det,dataOut_det,startOut_det,endOut_det,validOut_det,err);

dataIn, startIn, endIn, and validIn are input data and control signals to the HDL CRC generator. dataOut_gen (output of CRC generator) displays the message with the checksum appended every dataIn_width bits per sample. You can read the checksum when endOut_gen is high in the output waveform. The value 0x5B57 matches the CRC-16 FCS specified in 802.11 standard Section 15.2.3.6. dataIn_det shows the message with the corrupted checksum. dataOut_det displays the message output of the CRC detector. Error is detected when the err signal is high. err is valid when the endOut_det is active.

Initial delays are introduced at the output of the CRC generator and detector. You can calculate the initial delays using the following command:

 initial_delay_gen =  crc_len/dataIn_width + 2;
 initial_delay_det =  4*crc_len/dataIn_width + 4;

Check and Generate HDL Code

To check and generate HDL code of this example, you must have an HDL Coder™ license.

You can use the commands makehdl(subsystemname) and makehdltb(subsystemname) to generate the HDL code and testbench for the subsystems.

Specify the subsystem name as 'commcrchdl/CRC Subsystem/HDL CRC in Transmitter' or 'commcrchdl/CRC Subsystem/HDL CRC in Receiver'.

Selected References

IEEE 802.11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications. (2007 revision). IEEE-SA. 12 June 2007.
Giuseppe Campobello, Giuseppe Patane, Marco Russo. "Parallel CRC Realization," IEEE Transactions on Computers, vol. 52, no. 10, pp. 1312-1319, October, 2003.