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HDL Code Generation

Generate HDL code from MATLAB® code and Simulink® models

You can use HDL Coder™ features to implement communications system designs on FPGAs or ASICs. You can generate synthesizable and portable VHDL® and Verilog® code, and generate VHDL and Verilog test benches for quickly simulating, testing, and verifying the generated code. You can generate code from Simulink or MATLAB designs. This support includes error correction and detection, modulation, filters, mathematical and signal operations, and other algorithms optimized for resource use and performance, such as the NCO (DSP HDL Toolbox) block. For a basic example of how to generate HDL code, see Programmable FIR Filter for FPGA.

To debug your designs in Simulink or MATLAB, use the Logic Analyzer waveform viewer.

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Simulink Visualization Tool

Logic AnalyzerVisualize, measure, and analyze transitions and states over time

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