Algorithm Design to Hardware Deployment on FPGAs/SoCs using MATLAB and Simulink
Overview
This webinar explores Model-Based Design workflows using MATLAB and Simulink to speed development and deployment of algorithms on embedded hardware, with a focus on FPGAs and SoCs. It covers the end-to-end path from algorithm to implementation, including HDL code generation with HDL Coder and verification with HDL Verifier.
This session is for educators teaching courses on Digital VLSI Design using FPGAs/SoCs and researchers looking to deploy custom algorithms on embedded hardware. We will feature demos showcasing HDL code generation, verification, and FPGA-in-the-Loop (FIL), highlighting the efficiency and reliability of MATLAB and Simulink for development of applications on FPGAs/SoCs.
Highlights
Attendees will understand the use of MATLAB and Simulink to develop prototype and production applications for deployment on FPGAs and SoCs. We will:
- Introduce Model-Based Design for FPGA/SoC Embedded Systems
- Demonstrate HDL code generation from MATLAB & Simulink
- Optimize HDL code to meet Power, Performance, and Area (PPA) constraints
- Generate H/W utilization and traceability reports from MATLAB and Simulink
- Deploy generated HDL to an FPGA/SoC target from MATLAB and Simulink
- Verify implementation using FPGA-in-the-Loop (FIL) workflows
Who Should Attend
Professors, researchers and students.
About the Presenter
Dr. Praful Pai is the Manager, Electrical and Computer Engineering (ECE) at MathWorks. His focus is on developing MathWorks' approaches to technical areas including signal processing, wireless communications, and semiconductors through engagement with institutional leadership, faculty members, researchers, and students. He has worked extensively in multi-disciplinary teams focusing on mathematical modeling, signal and image processing, machine learning, hardware prototyping, and instrumentation.
