Videos

Verify VHDL ® and Verilog ® using HDL simulators and FPGA-in-the-loop test benches with HDL Verifier™.
This interactive, two-day course provides a guided workflow to generate and optimize your HDL code. Attend a course today and learn to generate and verify HDL code from a Simulink model using HDL...
This session demonstrates how recent developments in MATLAB ® and Simulink ® reduce the cost of developing FPGA and ASIC applications, through strong integration with...
Allegro Microsystems explains how they are leveraging MATLAB® and Simulink® for rapid prototyping, streamlined UVM-based verification, and automatic RTL code generation for...
Engineers complete communication payload design simulation and hardware validation and verification with Simulink® .
Perform FPGA-based verification with custom boards using MATLAB ® and Simulink ® as test benches. Figures based on or adapted from figures and text owned by Xilinx,...
Generate a SystemVerilog DPI-C reference model for use in UVM simulation from MATLAB ® using HDL Verifier™.
Insert test points into SystemVerilog DPI components generated by HDL Verifier™.
Perform FPGA-based verification with custom boards using MATLAB ® and Simulink ® as test benches. Figures based on or adapted from figures and text owned by Xilinx,...
Utilize the HDL Verifier™ FPGA-in-the-loop capability with PCI Express® for designs on an Altera® Cyclone® V GT FPGA development kit.
Utilize the HDL Verifier™ FPGA-in-the-loop capability with PCI Express® for designs on a Xilinx® Kintex® KC705 evaluation kit.