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HDL-Coder: initialization of internal VHDL-signals
All HDL Coder generated signals are fully initialized or driven with valid logic. Lack of valid drivers to signals is consid...

etwa 3 Jahre vor | 0

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How to create VHDL code of a Neural Network block created through GENSIM command ?
This example shows how to convert a neural network regression model (created using gensim) to HDL Code. https://www.mathworks...

etwa 3 Jahre vor | 0

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FPGA Synthesis and Analysis HDL coder
There are many reasons for the synthesis step to be taking a long time. If the generated HDL does not fit on the FPGA or very c...

etwa 3 Jahre vor | 0

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how can i use contiuous time integrator in hdl coder?
HDL Coder only generates code from discrete blocks. Continuous blocks are not supported. Consider using discrete time integrat...

etwa 3 Jahre vor | 0

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HDL work flow advisor for non evaluation board devices
https://www.mathworks.com/help/hdlcoder/create-a-custom-hardware-platform.html You can create your own custom reference desig...

etwa 3 Jahre vor | 0

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Compatibility of HDL coder with regression ensemble predict block and fixed point conversion
RegressionEnsemble Predict' block is currently not supported for HDL code generation. You need to build the block from first pr...

etwa 3 Jahre vor | 0

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Add 'MARK_DEBUG = "TRUE"' to signals in generated HDL
Currently synthesis attribute specification is limited to certain blocks like product block. This capability is planned for po...

etwa 3 Jahre vor | 0

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Is it possible to generate parametrized HDL for Chart parameters?
https://www.mathworks.com/matlabcentral/answers/382489-how-are-generics-supported-in-hdl-coder Currently type generics are not ...

etwa 3 Jahre vor | 0

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The function of generating HDL code has an error with the names of blocks in the same Subsystem
" ... in the subsystem "OFDM Transmitter" will contain the subsystem "whdlOFDMTx Model". When I do generate HDL code, the name o...

etwa 3 Jahre vor | 0

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Why I get this error when working with hdl workflow?
This is an unexpected error. Can you reach out to customer support with reproduction steps? Thanks.

etwa 3 Jahre vor | 1

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Synthesize Matlab function with large input and output onto FPGA
You have a large IO design (in frames); the design needs conversion to samples. Prior to R2022b release there was no automation ...

etwa 3 Jahre vor | 0

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Can't generate Simulink model from Simulink function block
https://www.mathworks.com/help/hdlcoder/ug/hdl-optimizations-across-matlab-function-simulink-blocks.html You can convert a subs...

etwa 3 Jahre vor | 0

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How to read a matrix data from a subfunction by HDLs coder
https://www.mathworks.com/matlabcentral/fileexchange/50098-hdlcoder-design-patterns-and-examples HDLCoder Design Patterns and E...

etwa 3 Jahre vor | 0

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how to configure parameters for NCO(frequency shifting or frequency correction) simulink block set based on the NCO operation has performed in the matlab script
Please find attached a sample NCO block that can generate HDL code.

etwa 3 Jahre vor | 0

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Deep Learning HDL Toolbox - Error using dnnfpga.compiler.codegenfpga Index exceeds the number of array elements. Index must not exceed 0.
This is not an expected error message. Please reach out to tech support for help and any available workaround.

etwa 3 Jahre vor | 0

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Error when converting design from Matlab Simulink to HDL
The model has an incorrect/undefined type specification. You need to use the fixdt(1,64,32) syntax. In addition, please n...

etwa 3 Jahre vor | 0

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HDL "complex to Magnitude and angle" module show critical path which can not meet 160MHz clock timing
Would you be able to share your model and HDL Coder code generation steps to reproduce the workflow?

etwa 3 Jahre vor | 0

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HDL Workflow Advisor - Step 3.2 - "Failed Index exceeds the number of array elements. Index must not exceed 2" in hdlturnkey.interface.ChannelBased/connectFrameInterfacePort
This is not an expected error message. Please reach out to tech support with reproduction steps.

etwa 3 Jahre vor | 1

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Converting Simulink Bus with mixed datatypes to an array of doubles
Can you share your current workaround? I wonder if this block would be of help in your usecase. Bus to Vector https://www.math...

etwa 3 Jahre vor | 0

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Simulink HDL Coder & Vitis Model Composer cannot find the same Device
Model Composer library in Simulink needs Vitis workflows to generate HDL Code. https://www.xilinx.com/products/design-tools/vit...

etwa 3 Jahre vor | 0

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How to initialize Dual rate Dual port ram?
RAM System object can be used as a block in Simulink and it supports Initial Value. The HDL library browser that ships with ...

etwa 3 Jahre vor | 0

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Why did I receive an error messageļ¼šISim engine error: Failed to Load up XSI.
Please try running with Vivado 2022.1. You can see our supported software in the documentation at: https://www.mathworks.com/hel...

etwa 3 Jahre vor | 0

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Simulink port annotations do not appear with HDL definition of wire/reg
I have reported the issue to the development team. As a workaround consider right-cliking on the port, choose port propert...

etwa 3 Jahre vor | 0

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How ro restore a fixed-pointed and saved model to its unfixed state?
>>I want to change some fuctions on its unfixed state. Do you mean the restore step in the Fixed-Point Tool failed for you a...

etwa 3 Jahre vor | 0

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DSP Builder HDL Import Design Example error
Please reach out to tech support. The error is coming from HDL Cosimulation block (probably you are using a HDL Verifer Cosimu...

etwa 3 Jahre vor | 0

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ip core generation stuck at hdl code generation step
Would you be able to share the MATLAB Code and the Project file? Please reach out to tech support for help.

etwa 3 Jahre vor | 0

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HDL Coder, Assertion failed: B:\matlab\src\cgir_hdl\dom_pir_core\dutinfo.cpp:101:portIdx < m_inportMap.size()
Can you share the model? This is not an expected error. Please reach out to MathWorks tech support and they can help you with ...

etwa 3 Jahre vor | 0

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implementing complex multiplication in simulink
For HDL Code Generation you can use the Simulink and MATLAB function examples shown below. These examples use FPGA/ASIC fri...

etwa 3 Jahre vor | 1

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HDL Coder cannot run HDL Code Generation
If you want to run a set of steps you need to right-click on the step and run to the task. It will run all the steps leading...

etwa 3 Jahre vor | 1

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How to generate testbench for a model whose input signals come from matlab workspace?
"Generate HDL Testbench" works on a subsystem with some stimulus and response and not the whole model. Mark the DUT "model/sub...

etwa 3 Jahre vor | 1

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