Community Profile

photo

Poorren


Last seen: 10 Tage vor |  Aktiv seit 2017

Followers: 0   Following: 0

Kontakt

Statistiken

  • Thankful Level 1
  • First Review

Abzeichen anzeigen

Feeds

Anzeigen nach

Frage


How to disable clockdriver logic and clr port (automatic added) in generated vhdl code?
The dev enviroment of my experiment is Matlab 2020b with Vivavdo 2020. I attached the sysgen model and relative configuration f...

7 Monate vor | 1 Antwort | 0

1

Antwort

Frage


tristate input in hdl verifier?
Hi guys, I met a problem on how to generate tristate bus stimulus in hdl verifier. In details, I need to verify a bus read/writ...

mehr als ein Jahr vor | 0 Antworten | 0

0

Antworten

Frage


How to update HDL verifier block when VHDL source changes its port definition?
I couldn't find a way to update the block when vhdl source change its source file. So, I have to manually add or remove those de...

mehr als ein Jahr vor | 2 Antworten | 0

2

Antworten

Frage


Exception on debug C shared library based application when using visual studio 2017
Hello guys, Now, I try and study to use Matlab library compiler to convert matlab script to library function, and call it in C ...

mehr als ein Jahr vor | 1 Antwort | 0

1

Antwort

Frage


Question on zp2sos gain scaling?
Hello guys, I have a question on matlab zp2sos function. The question is how matlab do scaling when convert z/p/k to zeros...

mehr als 6 Jahre vor | 0 Antworten | 0

0

Antworten