HDL Verifier Support Package for AMD FPGA and SoC Devices

Debug, test, and verify HDL code on AMD FPGAs, Zynq SoCs, and Versal Adaptive SoCs

HDL Verifier™ Support Package for AMD FPGA Boards and SoC Devices contains the board definition files for FPGA-in-the-Loop (FIL) simulation with HDL Verifier and supported boards with AMD FPGAs, Zynq SoCs, or Versal Adaptive SoCs.

• With FIL simulation, use MATLAB® or Simulink® to test designs on AMD devices for any existing HDL code.
• FPGA Data Capture support lets you observe signals from your design in MATLAB or Simulink while the design is running on the AMD FPGA or Zynq SoC.
• Using AXI Manager, you can read from or write to on-board memory locations using MATLAB or Simulink.

When using these tools, you can view signals in MATLAB using the Logic Analyzer window.