Error in importhdl how to solve?
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Nadatimuj
am 11 Feb. 2021
Bearbeitet: Stefanie Schwarz
am 5 Jan. 2022
I am trying to import a verilog module that calls other submodules. Whenever, I try to import from HDL to simulink, I am getting these errors. I don't even any clock in my design.
Module instance creation failed for 'x' module and 'y' module instance, due to clock inference limitation. Rerun with clock bundle name-value pair. More information.
Hdl Import parse failed.
Error using privimporthdl
Importhdl failed.
Error in importhdl (line 78)
privimporthdl(hdlInSrc, varargin{:}) - Show complete stack trace
2 Kommentare
Khalala Mamouri
am 23 Feb. 2021
Hello,
I currently facing the same issue; have you solved the problem ?
Best regards
lakhdar
Akzeptierte Antwort
Stefanie Schwarz
am 5 Jan. 2022
Bearbeitet: Stefanie Schwarz
am 5 Jan. 2022
Here is a list of supported constructs with importdhl:
If you encounter the same error, please contact MathWorks Technical Support with your Verilog source code so we can investigate.
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