How can I resolve the issue of sample time mismatch?

An error of 'sample time mismatch' happened during running a test environment which including control modules with fixed-step solver and plant model with varible-step solver. The block which mentioned in the error message use fixed-step slover(sample time is 0.01). The signal is trasferred from varible-step type to fixed-step type.

As follows is the error message.

Sample time mismatch. When a Bus Creator or Bus Assignment block outputs a nonvirtual bus, all of the signals driving its input ports must have the same sample time. This restriction applies even if the elements of the object defining the bus specify an inherited (-1) sample time. The sample time of the signal (0.02) driving input port 1 of 'MIL_Harness/Vehicle/Powertrain/Applications' does not match the sample time of the block (0.01).

[Vincent Nicolazzo]

I have this same problem. I have a system block that I am trying to turn into a stand alone model so I am able to generate C-code form. When I use a reference block (instead of a subsystem) I get this error.

I am only able to solve this problem by removing the reference block and using a standard subsystem. I believe the root of this error comes from having mulitple refrence blocks within each other.

Matlab's error does not clearly specify where the error occurs in the model so I have a hard time completly solving this issue.. Hope this input sparks additional thoughts on how to solve this problem.