How to remove unwanted sawtooth gating pulses for inverter

I am using space vector modulation to generate the switching signals for a 4 level inverters and the gating pulses for devices from the controller is that. Why instead of have a correct signals, it has sawtooth like that. The solver is ode4 (runge-kutta) 2e-6 seconds. I've found that the sawtooth frequency is equal the solver (1/2e-6 seconds). Thanks for help

Answer 1

[Jack]

The sawtooth gating pulses are an artifact of using a fixed-step solver with a step size of 2e-6 seconds. Since the solver updates the state only at these discrete intervals, the gating signals generated by space vector modulation are effectively “sampled” at 1/2e-6 Hz, leading to a sawtooth appearance.

To remove these unwanted pulses, you can try one or more of the following approaches:

• Decrease the solver step size further so that the switching transitions are captured more accurately.
• Use a different solver that better handles the rapid switching dynamics.
• Isolate the switching signal generation from the continuous simulation (for example, using dedicated discrete blocks or a Stateflow chart) so that the switching signals aren’t tied directly to the fixed-step integration.

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[Hoang Le]

Hi Jack,

Thank you for your answer. However, even I tried different solvers, the sawtooth was still there. My sampling time is just 1/1000 second, but the sawtooth has frequency of the step size 1/2e-6. I wonder if there are any other ways to sovle this problem. Thank you for help,

[Jack]

The sawtooth gating pulses may be occurring because your switching signals are being generated at the integration step (2e-6 sec) rather than at your intended sampling time (1/1000 sec). Even if you change the solver, if the blocks generating the switching signals are still tied to the integration steps, you'll see that artifact.

One solution is to decouple the switching signal generation from the continuous integration. For example, you can place the space vector modulation or the switching signal generation logic into a discrete subsystem with an explicit sample time (1/1000 sec). Using a Zero-Order Hold or a Rate Transition block between the continuous and discrete portions of your model will ensure that the gating pulses are updated only at the desired interval. This way, the discrete blocks generate a stable signal based on your specified sample time, preventing the sawtooth behavior caused by the ultra-small integration step.

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