Dual Port RAM System Verilog HDL code generation result cannot be compiled due to for loop limitation in Quartus

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When using Quartus to synthesize HDL generated from a Simulink model containing only Simple Dual Port RAM System blocks, the following error message appears.
I would like to know if there is a way to avoid this issue on the HDL Coder side.
The following error message from Quartus.
"Error (13356): Verilog HDL Loop error at SimpleDualPortRAM_generic.v(47): loop must terminate within 5000 iterations File: C:/Secret/MATLAB/support_request/20230926_c10gx_qproj_target_ram_for_loop/hdl_prj/hdlsrc/test_ram_model/SimpleDualPortRAM_generic.v Line: 47"

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MathWorks Support Team
MathWorks Support Team am 26 Sep. 2023
The iteration limit is set to 5000 by default in Quartus for initialization loops in Verilog. The name of the parameter that controls this value is 'Iteration limit for constant Verilog loops logic option' and can be found here - https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/logicops/logicops/def_verilog_constant_loop_limit.htm
On modifying the parameter to a value greater than the loop count, the error does not appear. If your model has the subsystem contains a RAM block whose address width is 16 bits, Since the Verilog code has a loop for initializing the values in the RAM, it loops through 65536 values in the RAM. 
In Quartus, this parameter can be found under Assignments -> Compiler Settings -> Advanced Settings (Synthesis)... -> Iteration limit for constant Verilog loops

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