Why is the output of the FFT HDL Optimized block zeros in Vivado's Simulation ?

I recently connected the FFT Block in Simulink to in and out ports so i can generate its HDL Code and implement it in Vivado.

After i generated it, i compiled the files in Vivado and created a block design to connect its inputs and outputs to other components of my design, but first i wanted to test if it's even working so i connected the data_in port to a simple counter and ran the simulation.

The output was unfortunately just a bunch of zeros (bit vector of 19 zeros).

Any idea why it behaves like this ?

(clk connected to clocking wizard, reset connected to "1" as a constant and so are valid_in and clk_enable also).

This screenshot is from Vivado's Block Design but this FFT IP's source is Simulinks/Matlab's generated HDL code of the FFT HDL Optimized Block.

Answer 1

[Bharath Venkataraman]

I'd first suggest that you run the generated HDL and Testbench to make sure that the HDL design is working correctly.

The next thing is to check and make sure that you are feeding in the correct data via data_in and that valid_in is staying high for the FFT length. Also, note that FFT has a latency, so the output will stay at 0s for a certain number of clock cycles after the last input of the frame is passed in.

Hope this helps.

[Youssef Abdelsalam]

First of all thanks for your answer,once again.

I tried to simulate the whole model (it's not something big i was just passing a sinewave through the FFT Block to see the output) but the output was also 0 in the simulation.

Does this have to do something with the fact that when i designed it simulink i didnt generate an input stimulus ? (the output of the testbench is also zeros, but this make sense because i didnt generate an input for the FFT in Simulink, but I did in Vivado and the output is still zeroes when i run the behavioral simulation.)

[Bharath Venkataraman]

I suggest that you generate an input stimulus in Simulink, pass it through the FFT subsystem to make sure that you are driving the input properly and getting the desired output. This gives you a working baseline in Simulink.

Once the above is done, you can check your Vivado design to make sure that your input in the Vivado design matches how you are driving your Simulink design.

[Youssef Abdelsalam]

Ok i will do that, thanks