Video Capture (software interface)

Capture video to ARM processor on a Zynq-based video system

Description

The Video Capture (software interface) block provides a video capture and control interface to the FPGA reference design included with this support package. Use this block in a software model to design and deploy generated ARM® code for image processing on the Zynq® device. You can create a model for software targeting using the default FPGA design loaded at setup. You can also customize the FPGA logic and use targeted software to interface with your FPGA design.

The HDL Workflow Advisor generates a software interface model that contains the Video Capture (software interface) block. The default parameter settings of the generated block match the settings of the Video Capture block in your original model. You can change the input video resolution, switch between HDMI input or an on-chip test pattern generator, and enable an optional bypass of the user logic section of the FPGA. When you change a parameter, the block writes an AXI-Lite register on the board. The dimmed parameters are for informational purposes only.

When you use this block in a model deployed with the default FPGA image, you can change the video format that is imported to the ARM processor.

The FPGA user logic section is the IP core that you generate from your design using HDL Workflow Advisor. If you enable the bypass of the FPGA user logic, the HDMI output is the same as the HDMI input. Points A and B in the diagram show the options for capturing video into the ARM processor.

The video data is a pixel stream on the FPGA. When you route the video data to the ARM processor, it is converted to frame-based video.

Required Products

To use the Video Capture (software interface) block in either the generated model or a model you create yourself, these products are required:

  • Embedded Coder®

  • Embedded Coder Support Package for Xilinx® Zynq Platform

Dialog Box and Parameters

Video source

The video stream through the FPGA logic and ARM processor can start with input video from the camera board’s HDMI port or with generated video from the test pattern generator. This parameter is tunable.

  • HDMI input (default) — HDMI input port on the FMC-HDMI-CAM board. Select a Frame size to match the resolution of your attached camera.

  • Test pattern generator — On-chip test pattern generator (TPG).

    The TPG creates input frames at the requested resolution. The test pattern is a fixed colorbar pattern. When you select TPG, you do not need a camera or other HDMI source connected to the board.

Frame size

Resolution of the input video. Select from HD and SD TV resolutions, and from many common computer frame sizes. If the resolution you select does not match the resolution of the HDMI input source, the block returns an error. The supported frame sizes are:

  • 480p SDTV (720x480p)

  • 576p SDTV (720x576p)

  • 720p HDTV (1280x720p)

  • 1080p HDTV (1920x1080p)

  • 640x480p

  • 800x600p

  • 1024x768p

  • 1280x768p

  • 1280x1024p

  • 1360x768p

  • 1400x1050p

  • 1600x1200p

  • 1680x1050p

  • 1920x1200p

Frame rate

Rate at which consecutive images are displayed (frames per second). For most frame sizes, this parameter is informational. Frame size 576p supports only 50 fps. Most other frame sizes support only 60 fps, except for 720p and 1080p.

When you use frame sizes 720p or 1080p, you can select from these frame rates:

  • 24 fps

  • 25 fps

  • 30 fps

  • 50 fps

  • 60 fps

The block sets the Simulink® sample time for the captured video frames to 1/Frame rate.

Pixel format

Pixel component representation. When you customize the FPGA user logic, this parameter is informational only. In the generated software interface model, this parameter displays the configuration you selected in the Video Capture block before you generated HDL code. When you use the default FPGA logic, you can select any pixel format.

  • RGB — Three 8-bit color components per pixel, which is 24 bits per pixel total. When you select RGB, you can also select the color space conversion standard and whether the block output is a multidimensional signal or three separate color signals. See the Use color space conversion specified by and Image signal parameters, respectively.

  • Y only — Grayscale. One 8-bit component per pixel.

  • YCbCr 4:2:2 (default) — Also known as YUYV. An 8-bit Y component and an interleaved 8-bit CbCr component. The effective pixel size is 16 bits.

Use color space conversion specified by

Specify the standard for conversion between RGB and YCbCr color spaces: Rec. 601 (SDTV) or Rec. 709 (HDTV). When you customize the FPGA user logic, this parameter is informational only. The block displays this parameter when you set Pixel format to RGB.

Bypass FPGA user logic

Select this check box to bypass the user logic section of the FPGA and send the input video frames directly to the HDMI output. When you select this option, capture point A and B observe the same video data. This parameter is tunable.

Capture point

You can import frames to the ARM processor from the input or output of the user logic section of the FPGA. This section of logic is a pass-through in the default FPGA image. Capture points A and B are shown in the data path diagram in the Description section of this page.

  • Input to FPGA user logic (A) — Capture frames after conversion and before the user logic section.

  • Output from FPGA user logic (B) — Capture frames after the user logic section and before conversion back to HDMI output.

  • No capture — No video data is passed to the ARM processor. You can still use the block to control the video options on the FPGA.

Image signal

For RGB data, choose whether to output a single 3-by-height-by-width matrix, or separate height-by-width matrices for each color. The default is Separate color signals. You can also select One multidimensional signal. To enable this parameter, set Pixel format to RGB.

Introduced in R2016a