Video Capture

Import live video frames from Zynq-based system


The Video Capture block imports video frames from a Zynq®-based board into your Simulink® model. The support package programs the FPGA with an image that includes data path multiplexers, video format conversions, and a video test pattern generator (TPG). You can control these data path and conversion options from the Video Capture block.

Points A and B in the diagram show the options for capturing video into Simulink. The FPGA user logic section is the IP core that you generate from your design using HDL Workflow Advisor. You can capture the input video before the FPGA user logic, or the output video after the FPGA user logic. If you enable the bypass of the FPGA user logic, the two capture locations show the same data.

The video data is a pixel stream on the FPGA, but when routed to Simulink, it is converted to frame-based video.

The reference design requires the same video resolution and color format for the entire data path. The resolution you select on the Video Capture block must match that of your camera input. The design you target to the FPGA user logic must not modify the frame size or format of the data.


Video source

The video stream through the FPGA logic and ARM® processor can start with input video from the camera board’s HDMI port or with generated video from the test pattern generator.

  • HDMI input (default) — HDMI input port on the FMC-HDMI-CAM board. Select a Frame size to match the resolution of your attached camera.

  • Test pattern generator — On-chip test pattern generator (TPG).

    The TPG creates input frames at the requested resolution. The test pattern is a fixed colorbar pattern. When you select TPG, you do not need a camera or other HDMI source connected to the board. The FMC card is still required.

Frame size

Resolution of the input video. Select from HD and SD TV resolutions, and from many common computer frame sizes. If the resolution you select does not match the resolution of the HDMI input source, the block returns an error. The supported frame sizes are:

  • 480p SDTV (720x480p)

  • 576p SDTV (720x576p)

  • 720p HDTV (1280x720p)

  • 1080p HDTV (1920x1080p)

  • 640x480p

  • 800x600p

  • 1024x768p

  • 1280x768p

  • 1280x1024p

  • 1360x768p

  • 1400x1050p

  • 1600x1200p

  • 1680x1050p

  • 1920x1200p

Frame rate

Rate at which consecutive images are displayed (frames per second). For most frame sizes, this parameter is informational. Frame size 576p supports only 50 fps. Most other frame sizes support only 60 fps, except for 720p and 1080p.

When you use frame sizes 720p or 1080p, you can select from these frame rates:

  • 24 fps

  • 25 fps

  • 30 fps

  • 50 fps

  • 60 fps

The block sets the Simulink sample time for the captured video frames to 1/Frame rate.

Pixel format

Pixel component representation. You can convert the input video to one of the following:

  • RGB — Three 8-bit color components per pixel, which is 24 bits per pixel total. When you select RGB, you can also select the color space conversion standard and whether the block output is a multidimensional signal or three separate color signals. See the Use color space conversion specified by and Image signal parameters, respectively.

  • Y only — Grayscale. One 8-bit component per pixel.

  • YCbCr 4:2:2 (default) — Also known as YUYV. An 8-bit Y component and an interleaved 8-bit CbCr component. The effective pixel size is 16 bits.

The HDMI input video on the Zynq boards is delivered in YCbCr 4:2:2 format. Your configuration of the Video Capture block sends control signals to the FPGA. The FPGA logic converts the input and output data according to the pixel format you specify.

Pixel FormatFPGA Logic Action
YCbCr 4:2:2 (YUYV)Passes through.

Converts HDMI input pixels from YCbCr 4:2:2 to RGB, and converts from RGB to YCbCr 4:2:2 for the HDMI output.

Y only

Uses the Y component of HDMI input pixels in YCbCr 4:2:2, and outputs the Y component of YCbCr 4:2:2 for the HDMI output.

Use color space conversion specified by

Specify the standard for conversion between RGB and YCbCr color spaces: Rec. 601 (SDTV) or Rec. 709 (HDTV). To enable this parameter, set Video pixel format to RGB.

Bypass FPGA user logic

Select this check box to bypass the user logic section of the FPGA and send the input video frames directly to the HDMI output. When you select this option, capture point A and B observe the same video data.

Capture point

You can import frames to Simulink from the input or output of the user logic section of the FPGA. This section of logic is a pass-through in the default FPGA image. Generate HDL from your Simulink subsystem to insert into the user logic section of the FPGA. Capture points A and B are shown in the data path diagram in the Description section of this page.

  • Input to FPGA user logic (A) — Capture frames after conversion and before the user logic section.

  • Output from FPGA user logic (B) — Capture frames after the user logic section and before conversion back to HDMI output.

  • No capture — No video data is passed to Simulink. You can still use the block to control the data path and video format on the FPGA.

Image signal

For RGB data, choose whether to output a single 3-by-height-by-width matrix, or separate height-by-width matrices for each color. The default is Separate color signals. You can also select One multidimensional signal. To enable this parameter, set Pixel format to RGB.

Introduced in R2016a