Models Generated from FPGA Targeting

The HDL Workflow Advisor generates two models: a hardware interface model and a software interface model. It also generates two libraries that contain the interface blocks used in the generated models.

The software interface model and its library are generated only if you have Embedded Coder® and Embedded Coder Support Package for Xilinx® Zynq® Platform installed. To generate the software interface model and library, you must also have run the setup steps described in Setup for ARM Targeting.

  • You can use the hardware interface model to control the reference design on the board, including your FPGA user logic, from the Simulink® model, without Embedded Coder.

  • The software interface model supports full software targeting to the Zynq hardware, including:

    • External mode simulation

    • Processor-in-the-loop

    • Full deployment

Save the generated models and libraries after generation. When you regenerate the library interface blocks, any changes, such as adding an AXI-Lite port, propagate to the saved models the next time you open them. Save the updated library over the previous library model to propagate the changes to existing interface models. If you do not want to update previous models, save the new generated library with a new name.

The models and libraries shown here are generated from the Developing Vision Algorithms for Zynq-Based Hardware example model.

Hardware Interface Model and Library

Use the generated hardware interface model to develop Simulink algorithms that use the captured video data from the FPGA as it running on the board. This model enables you to target all or part of your video processing design to the FPGA, while doing parallel, or subsequent processing in Simulink. You can control the parameters on the Video Capture block, and read or write any AXI-Lite ports you specified on your FPGA user logic. Changes to the block or port values modify the behavior of the reference design on the board, in real time.

In the top shaded area, Vision Zynq Device to Simulink Algorithm, you can add algorithms to operate on the captured video data. You can modify the parameters on the Video Capture block to control the format and capture location of the input video frames.

In the bottom shaded area, Simulink Interface to HW User Logic, you can add algorithms to write or read the AXI-Lite registers you specified as ports on your targeted subsystem.

The HDL Workflow Advisor also generates a library that contains these two interface blocks.

Software Interface Model and Library

This model enables you to target video processing and control algorithms to the ARM® processor on the board. Deploy code generated from this model to the board to run along with the FPGA user logic.

Use this model to:

  • Import video frames to the ARM processor.

  • Control the FPGA data path by changing the parameters on the Video Capture (software interface) block.

  • Read or write any AXI-Lite ports you have specified on your FPGA user logic.

The top shaded area, ARM Interface to Vision Zynq Device, contains a Video Capture (software interface) block. This block imports video frames to the ARM processor. You can also control the input video resolution, switch between HDMI input or an on-chip test pattern generator, and enable an optional bypass of the user-designed section of the FPGA logic. When you change a parameter in this block mask, the block writes an AXI-Lite register on the board. The dimmed parameters are for informational purposes only. The video format is fixed, because the FPGA user logic is running on the board with the data format you specified when you generated HDL code.

In the bottom shaded area, Simulink Interface to HW User Logic, you can add algorithms to write or read the AXI-Lite registers you specified as ports on your targeted subsystem. You can generate ARM code from this section of the model and run it in external mode. Alternatively, you can fully deploy the code to the board.

The HDL Workflow Advisor also generates a library that contains these two interface blocks.

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