FPGA targeting starts when you generate HDL code to represent a subsystem in your design. To support HDL code generation, the subsystem must be designed with hardware implementation in mind. Hardware vision processing applications use a pixel-streaming interface rather than frame-based video. From the generated code, the software creates a custom image for the FPGA fabric. This custom bitstream is then downloaded to the FPGA on the development board. This procedure enables you to implement your custom algorithm on the Zynq® development hardware, providing the following advantages:
By moving part of or all your algorithm to the hardware, you speed up the host processing.
You can also use FPGA targeting for prototyping designs on real hardware.
In addition to generating and deploying the FPGA image, the FPGA targeting workflow generates two Simulink® models: a hardware interface model and a software interface model. The tool also creates two libraries that contain the interface blocks used in these two models. If you do not have Embedded Coder® installed, the software interface model and its associated library are not created.
The hardware interface model can be used to control the reference design from the Simulink model without Embedded Coder. The software interface model supports software targeting to the ARM® processor on the Zynq device, using Embedded Coder.
To generate the hardware interface model, these products are required:
HDL Coder Support Package for Xilinx® Zynq Platform
To generate the software interface model, these products are required:
Embedded Coder Support Package for Xilinx Zynq Platform
Open the model that contains the Video Capture block and the subsystem you are targeting for your Zynq device.
In preparation for targeting, set up the Xilinx tool chain by calling the
function. For example:
C:\Vivado\2018.2\bin\vivado.bat with the correct path
for your Vivado® installation.
Make sure that your vision hardware is connected to and communicating with the host computer.
If you are unsure if your vision hardware is connected correctly and communicating with the host computer, you can run the Getting Started with Vision Zynq Hardware example to check the connection.
Start the HDL Workflow Advisor by right-clicking the subsystem that contains the algorithm and selecting HDL Code > HDL Workflow Advisor.
In the left pane, click 1. Set Target.
Click 1.1 Set Target Device and Synthesis Tool and set these options:
Target platform: Select your vision hardware.
Project folder: Accept the default, or enter a valid path for the location of your project folder.
All other fields are populated automatically.
Click 1.2 Set Target Reference Design and set these options:
Select a reference design according to the pixel format that the FPGA user logic expects. Options are:
RGB — Three 8-bit color
components per pixel, which is 24 bits per pixel total.
Y only — Similar to
intensity, but with a range of [16, 235]. One 8-bit
component per pixel.
YCbCr 4:2:2 — YUYV. The
data range for Y is [16, 235], and the range for Cb and Cr
is [16, 240]. Consists of an 8-bit Y component and an
interleaved 8-bit CbCr component. The effective pixel size
is 16 bits.
Source Video Resolution
Optionally, select the resolution of your input video. The tool calculates the necessary clock frequency to support the resolution you select, and adds a synthesis constraint. By default, the design is synthesized using a clock constraint of 148.5 MHz on the HDMI pixel clock. This rate supports a maximum resolution of 1080p HDTV at 60 frames-per-second.
After step 4.3, check the synthesis logs for your design to verify that the synthesis achieved the requested clock frequency.
Do not modify DUT Synthesis Frequency directly. The value is overwritten by the calculated value based on the selected resolution.
The resolution of the output video stream from the FPGA user logic must match the resolution of the input video. You cannot change the dimensions of the video within the FPGA user logic.
Click 1.3 Set Target Interface and map the ports of your subsystem to available hardware interfaces provided by the reference design.
ctrl bus ports to the custom
Pixel Control Bus Input and
Pixel Control Bus Output interfaces.
The signals are flattened in the generated HDL code.
If your design uses external memory, map the related ports to
either frame buffer or AXI Master interfaces. For a frame buffer,
map the write interface to
Master and the read interface to
Frame Buffer Slave. For random
access, map the write interface ports to
Write and the read interface ports to
AXI4 Master Read. For more detail,
see Model Frame Buffer Interface and Model AXI Master Interface.
Processor/FPGA synchronization must be set to
Free running (default).
Coprocessing mode is not
Click 2. Prepare Model for HDL Code Generation. Run all tasks through 2.4. If any task fails or warns, try to correct the issue. You cannot continue until you resolve any problems.
If you are already familiar with preparation and HDL code generation phases, you can right-click step 4.1 and select Run to selected task. You do not need to modify settings in step 3.
In Step 3.1.2, you cannot select an Oversampling factor other than 1.
In step 4.2, click Run This Task. The HDL Workflow Advisor generates these models and libraries:
A hardware interface model and a library that contains the interface blocks from this model.
A software interface model and a library that contains the interface blocks from this model, if the Embedded Coder Support Package for Xilinx Zynq Platform support package is installed. You must also have run the manual setup steps in Setup for ARM Targeting.
For more information about these models and libraries, see Models Generated from FPGA Targeting.
In step 4.3, the HDL Workflow Advisor generates a programming file for the FPGA. To execute this step in an external shell so that you can continue to use MATLAB® while the FPGA builds, keep the selection Run build process externally. The build can take 20 minutes or more to complete. When the build is finished, a message in the command window lets you know that you can close the window.
After the HDL Workflow Advisor completes some basic project checks, it shows this step as completed while the FPGA is still being built. Wait until the external shell shows a successful image build before moving on to the next step.
In step 4.4, to download the completed FPGA image to the target hardware,
select Run This Task. All prior tasks must have a
Warning. This step
renames the generated bitstream file and moves it to the
You can manually download any bitstream file from this directory to the target hardware by running these commands:
vz = visionzynq(); downloadImage(vz,'BITSTREAM_NAME.bit');