This example shows how to design a data path for a Xilinx® RFSoC device by using SoC Blockset®. You will design and simulate a system that generates a sinusoidal tone from an FPGA and transmit the tone across multiple RF channels by using the RF Data Converter (RFDC) block. The system will then receive the data back into the FPGA by using the RFDC block and visualizes the received tone for one channel at a time by using an embedded processor.
Consider a wireless application that requires accessing multiple RF channels at giga samples per second (GSPS) data rate in duplex mode on the Xilinx RFSoC device. In this example, the design task is to generate a sinusoid tone from the FPGA, configure the RFDC block, and receive the data back into the FPGA on ZCU111 and ZCU216 evaluation kits with the following system specifications.
System Specifications for ZCU111 Evaluation Kit
ADC and DAC sampling rate = 2048 MSPS
Number of ADC Channels = 8
Number of DAC Channels = 8
Digital data interface = Real
System Specifications for ZCU216 Evaluation Kit
ADC and DAC sampling rate = 1024 MSPS
Number of ADC Channels = 16
Number of DAC Channels = 16
Digital data interface = IQ
Design and implementation of the above system presents the following challenges:
Configuring multiple parameter values of the RFDC block to meet the system requirement is difficult.
Designing the algorithm in an FPGA to operate multiple samples at a time increases the design complexity due to high data rate.
Designing the data path from an FPGA to a processor to meet a given system requirement is difficult, given the asynchronous nature of FPGA and processor.
By modeling the system using the RF Data Converter block and external memory blocks, provided by SoC Blockset, you will simulate the design before implementation. Simulating the design enables you to identify and fix the issues in the Simulink, prior to implementation on the hardware.
This design example contains two top models.
soc_rfsoc_datacapture - Capture real data with 8 channels on ZCU111 evaluation kit
soc_rfsoc_IQ_datacapture_top - Capture complex IQ data with 16 channels on ZCU216 evaluation kit
This example shows the workflow using the
soc_rfsoc_datacapture model. The workflow steps are common for both the models.
Create an SoC model
soc_rfsoc_datacapture as the top model and set the Hardware Board option to
Xilinx Zynq Ultrascale+ RFSoC ZCU111 Evaluation Kit . This model includes the FPGA model
soc_rfsoc_datacapture_fpga and the processor model
soc_rfsoc_datacapture_proc instantiated as model references. The top model also includes Memory Channel and Memory Controller blocks that share the external memory between the FPGA and the processor.
RF Data Converter Configuration
RF Data Converter block provides an RF data path interface to the wireless algorithm modeled in the hardware logic. You can use this block to model and configure the ADCs and DACs and connect the data from and to the hardware logic. The block provides an interface to the Xilinx RF Data Converter IP in Simulink for modeling a wireless system destined for implementation on Xilinx RFSoC device.
To meet the system requirement of 2048 MSPS as the data rate for DACs and ADCs, you must choose the values of Interpolation mode, Decimation mode, and Samples per clock cycle parameters such that the effective clock cycle (sample rate) for the wireless algorithm FPGA is in the desirable range. This is calculated as below and is displayed on the block as Stream clock frequency after you click Apply.
For this example, in the DAC tab, set the Interpolation mode and Samples per clock cycle parameter values to 4 and in the ADC tab, set the Decimation mode and Samples per clock cycle parameter values to 4. This implies the Stream clock frequency to be 2048/(4*4) = 128 MHz.
The RF Data Converter block provides output ports for DAC (dac1, dac2, and so on up to dac8) and input ports for ADC (adc1, adc2, and so on up to adc8) on the left side. The left-side port signals are vectorized version of the corresponding right-side signals that are connected to the FPGA. For this example, the right-side DAC and ADC signals (dac1Data, dac2Data, and so on up to dac8Data and adc1Data, adc2Data, and so on up to adc8Data) are 64 bits wide each (uint64) and the left-side signals are 4x1 int16 vector version of the corresponding right-side signal. If required, these ports can be used to model the data path after the ADC and DAC for wireless channel. For this example, connect the DAC signals to the ADC signals for looping back the transmitted signals.
Hardware Logic Design
To match the DAC digital interface of the RF Data Converter block, the transmit path of the hardware logic must send four samples per cycle of 128 MHz clock. This figure shows the data interface for one of the eight DAC data interfaces of the RF Data Converter block. The sample rate for the sinusoid tone generation is 512 MSPS (128 x 4).
Similarly, on the receive side the algorithm must operate on 4 samples per clock cycle. This figure shows the data interface for one of the eight ADC data interfaces of the RF Data converter block.
The FPGA model soc_rfsoc_datacapture_fpga contains two subsystems, DAC Tone Generation connected to the DAC portion of the RFDC block and the ADC Capture subsystem connected to the ADC portion. Four consecutive samples of the sinusoid waveform are generated in parallel by using four HDL Optimized NCO blocks and choosing a different offset for each HDL Optimized NCO block. All four samples are packed together as 64 bits data as AXI-Stream data width. In addition, the same waveform is transmitted across all the eight channels. Each channel is scaled by a different scaling factor set as a register from the processor.
In the ADC Capture subsystem, one of the eight channels is selected using a register set by the processor. The data from the selected channel is downsampled by 128 before sending it to the processor.
Processor Logic Design
The processor logic contains an event-based task driven by the arrival of data from the FPGA through DDR memory. The processor algorithm task is denoted as dataTask in the Task Manager block and is specified as event-driven. The Task Manager block schedules data asynchronously by means of a buffer ready event, rdEvent in the memory channel denoting an arrival of a frame of data from FPGA. The algorithm itself is modeled under Processor Algorithm Wrapper subsystem in the processor model soc_rfsoc_datacapture_proc and connected to the Task Manager block at the top level. To operate on the data received as a frame of packed 4 samples as uint64, it is required to first unpack and restore the signedness of the data. The output of the processor Algorithm subsystem is then connected to Spectrum and Time scope for visualization. In a separate Initialize Function subsystem various registers on the FPGA subsystems are initialized with their default values.
Run the model and visualize the sinusoid tone generated from the FPGA on spectrum analyzer scope titled as DAC Output.
The waveform is looped back from the FPGA to the processor through RFDC block, ADC Capture subsystem in FPGA and the memory blocks. In the processor system it is visualized in the frequency domain using a Spectrum scope block titled as ADC Captured Signal. The signal is also observed in the time domain using a Time scope block titled ADC Captured Scope Output. The data is observed on these scopes with a substantial delay after the simulation has started. This is because of the delay in the availability of the first frame of data by the scopes due to long loop back data path.
Observe that both the transmitted and received signal show a tone of 0.5 MHz.
adcChannelSelect parameter to
5 from the command window as shown below to capture the data from the fifth channel. Run the simulation again and notice that the peak of the spectrum on ADC captured Signal scope is about 91.245 dBm as compared to 100 dBm for Channel 1. Similarly, notice that the amplitude of the time domain signal is reduced to 1578 from 4000 for Channel 1.
adcChannelSelect = 5;
To capture complex IQ data with 16 channels on ZCU216 evaluation kit, create an SoC model
soc_rfsoc_IQ_datacapture_top as the top model and set the Hardware Board option to
Xilinx Zynq Ultrascale+ RFSoC ZCU216 Evaluation Kit . This model includes the FPGA model
soc_rfsoc_IQ_datacapture_fpga and the processor model
soc_rfsoc_IQ_datacapture_proc instantiated as model references. Follow the steps mentioned in the previous sections, RF Data Converter Configurations, Hardware Logic Design, and Processor Logic Design by doing the following changes.
To meet the system requirement of 1024 MSPS, set the value of Interpolation mode on the DAC tab and the Decimation mode on the ADC tab of RFDC block to 40. Set the Samples per clock cycle on the ADC tab and the DAC tab to 2. This implies the Stream clock frequency to be 1024/(40*2) = 12.8 MHz. Set the NCO frequency to 0.5 GHz and NCO phase to 0 for all 16 channels.
To match the DAC digital interface of the RF Data Converter block, the transmit path of the hardware logic must send two samples per cycle of 12.8 MHz clock. This figure shows the data interface for one of the sixteen DAC IQ data interfaces of the RF Data Converter block. The sample rate for the complex sinusoid tone generation is 25.6 MSPS (12.8 x 2).
Similarly, on the receive side the algorithm must operate on 2 samples per clock cycle. This figure shows the data interface for one of the sixteen ADC IQ data interfaces of the RF Data converter block.
Run the model and visualize the ADC captured sinusoid tone on spectrum analyzer.
This example demonstrated how to design the data paths involving the RF Data Converter on the Xilinx RFSoC device. You designed a system that generated a sinusoid waveform with multiple samples per clock and configured the RFDC block to transmit at the higher digital data rate of 2048 MSPS for real data and 1024 MSPS for IQ data. You also designed the data path to receive the transmitted samples back into the device and verified the waveforms by simulation. To verify the results on the hardware, see Transmit and Receive a Tone Using Xilinx RFSoC Device - Part 2 Deployment. You can follow the above design procedure to model any other high data rate wireless algorithm for Xilinx RFSoC Device.