Transmit Signal Waveform Using DDR4 on Xilinx RFSoC Device
This example shows how to design and implement a hardware algorithm, which writes the 5G signal waveform data from processor into the DDR4 memory, reads continuously using transmit repeat, and sends to digital-to-analog converter (DAC), on an FPGA fabric by using the RFSoC support for a fixed reference design workflow. This example simulates hardware-software interaction and performs system-level simulation with the memory. This example generates HDL code for the algorithm as an IP core and integrates it in a reference design to build a system. Then, the example deploys the system to hardware and displays the received signal in Simulink®.
This example supports these hardware platforms:
Xilinx® Zynq® UltraScale+™ RFSoC ZCU111 evaluation kit and XM500 balun card
Xilinx Zynq UltraScale+ RFSoC ZCU216 evaluation kit and XM655 balun card
Using the Support for Fixed Reference Design workflow, you can focus on the algorithm component and integrate it in a predefined reference design that defines the architecture. Use this workflow for rapid prototyping when a reference design that meets your system requirements is available for deployment.
Modeling in this example is similar to modeling an algorithm with architecture, such as by using external memory and input/output (I/O) in Simulink but with a fixed referenced design. For an example that shows how to model the algorithm and FPGA or SoC architecture and that shows the workflow to design and implement the complete SoC model, see Transmit and Receive Tone Using Xilinx RFSoC Device - Part 1 System Design.
In this example, the Stream Write block transmits a 5G signal waveform as workspace data from the processor to PL DDR4 external memory. The hardware algorithm reads DDR4 data continuously and sends that data to the DAC channel of the RFSoC device. Then the signal waveform is received back from the analog-to-digital converter (ADC) channel in the FPGA. The receive-side FPGA receives logic to capture data and sends data to processor memory through the Stream Read block. Then the received data from memory is visualized in Simulink using the software model running on hardware in external mode.
This example contains two models. Both the models transmit a 5G signal waveform.
soc_waveform_tx_zcu111_top— Transmit a signal waveform on the ZCU111 board.
soc_waveform_tx_zcu216_top— Transmit a signal waveform on the ZCU216 board.
This example shows the workflow using the
soc_waveform_tx_zcu111_top model. The workflow steps are similar for both the models.
To work with the RFSoC support for a fixed reference design workflow, you must install and configure additional support packages and third-party tools. For more information, see SoC Blockset Support Package for Xilinx Devices.
Design Hardware Algorithm
To design the hardware algorithm, you must choose the reference design that meets your requirements by using the SoC Model Creator tool. To open this tool, enter this command at the MATLAB command prompt.
To create the model, follow these steps in the SoC Model Creator tool.
Select Reference design board as
Xilinx Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit.
Select Reference design name as
IQ ADC/DAC Interface.
Set Top model name to
Select the model type as FPGA and processor.
Set required reference design parameters in the Reference Design Parameters pane.
Select required interfaces in the Internal Interfaces pane.
Select required interfaces in the External IO Interfaces pane.
Add required registers in the AXI Registers pane.
The tool generates the
soc_waveform_tx_zcu111 top model,
soc_waveform_tx_zcu111_fpga FPGA model, and
soc_waveform_tx_zcu111_proc processor model. The subsystem in the FPGA model is preconfigured with ports to match your specified reference design. You can add your hardware algorithm in the FPGA model for hardware targeting and software algorithm in the processor model for software targeting. To simulate your algorithms, add stimuli and scopes in the top model. The
soc_waveform_tx_zcu111_fpga model is the hardware generation model that writes the received data from the processor into the DDR4 memory, reads DDR4 data continuously using transmit repeat logic, and sends read data to the DAC channel.
Simulate the model and observe the DAC spectrum plot in the
PlotDACData testbench subsystem for the transmitted 5G signal waveform of 100 MHz signal bandwidth and for the ADC captured signal waveform from the processor output.
Implement and Run on Hardware
Set the DUT subsystem of the FPGA model as an atomic subsystem by right-clicking the top-level DUT design subsystem
DAC_DDR4_Transmit and selecting Block Parameters (Subsystem) and Treat as atomic unit. Next, set up the Vivado tool version by using this command (which assumes that Xilinx Vivado® is installed at
To implement the model on a supported SoC board, use the SoC Builder tool. Before using this tool, ensure that the Hardware Board parameter is set to
Xilinx Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit on the System on Chip tab of the Simulink Toolstrip.
To open SoC Builder, click Configure, Build, & Deploy. After the SoC Builder tool opens, follow these steps.
On the Setup screen, select Build using fixed reference design. Click Next.
On the Review Task Map screen, click Next.
On the Review Memory Map screen, view the memory map by clicking View/Edit. Click Next.
On the Select Project Folder screen, specify the project folder. Click Next.
On the Select Build Action screen, select Build and load for external mode. Click Next.
On the Validate Model screen, check the compatibility of the model for implementation by clicking Validate. Click Next.
On the Build Model screen, begin building the model by clicking Build. An external shell opens when FPGA synthesis begins. Click Next.
On the Connect Hardware screen, test the connectivity of the host computer with the SoC board by clicking Test Connection. To go to the Load Bitstream screen, click Next.
The Build step integrates the newly generated IP core into the RFSoC IP core reference design, generates the corresponding embedded system with bitstream, and generates a software interface library and a software interface model.
On the Load Bitstream screen, load the bitstream onto the hardware by clicking Load. This action loads the bitstream and opens the software model in external mode.
Hardware Setup for ZCU111 Board
To complete the loopback between the DAC and ADC channels, connect the SMA connectors on the XM500 balun card according to this connect: DAC229_T1_CH2(J5) to ADC224_T0_CH0(J4).
After the bit file is loaded, open the generated software model and follow these steps.
Copy the spectrum analyzer from the top model, and connect the spectrum analyzer to the Unpack data block as the next figure shows.
Open Configuration Parameters window by clicking Hardware Settings on the System on Chip tab of the Simulink Toolstrip. In the Configuration Parameters window, in the Hardware board settings section, expand Target hardware resources. Under Groups, click External mode. Specify the IP address for your
XCP on TCP/IPcommunication interface as a dotted-quad value.
Copy the binary file
5GNRWave.binfrom the current directory to the target by using following commands. Ensure that the correct hardware board IP address is used while creating the hardware board object.
hwObj = socHardwareBoard('Xilinx Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit',"hostname",'192.168.1.101',"username",'root',"password",'root'); hwObj.putFile('5GNRWave.bin', '/mnt/5GNRWave.bin');
Run the software model in external mode. The spectrum analyzer shows the 5G signal waveform of the ADC channel.
Implement and Run Example Model on ZCU216 Board
To generate the IP core and run the
soc_waveform_tx_zcu216_top model on a ZCU216 board, follow the SoC Builder tool steps mentioned in the previous sections of this example and use this hardware setup for connections.
Run the corresponding software model in external mode to see the ADC-captured 5G signal waveform.
Procedure to Send Waveform
Generate a waveform from any waveform app or use your own generated waveform signal.
Ensure that the waveform samples are complex.
Assign the waveform samples data to the variable
Run the script
Implement an algorithm that writes and reads the 5G waveform signal data into PL DDR4 memory and sends data continuously to DAC for transmission. Loop back the transmitted signal to the ADC and receive it back into the FPGA on an RFSoC device. Verify that the system works as expected on the hardware. You can use this example as a reference and prototype for your wireless algorithm to send any waveform signal on the Xilinx Zynq UltraScale+ RFSoC ZCU111 evaluation kit or Xilinx Zynq UltraScale+ RFSoC ZCU216 evaluation kit.
- Memory Controller | Memory Channel | Register Channel | Register Write | Stream Read | Stream Write | Task Manager