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Support for Fixed Reference Design

Create SoC model for fixed reference design, edit created model to include algorithm, simulate and/or build and deploy model on MPSoC and RFSoC devices

This workflow enables algorithm and system designers to generate an HDL IP core and integrate it into a fixed reference design for rapid prototyping. Create an SoC model based on the selected reference design for the supported Xilinx® MPSoC and RFSoC devices by using the SoC Model Creator tool. Use the created model as a template to design and simulate your FPGA algorithm and processor algorithm. Then, generate a bitstream and host I/O model, build a software application, and program the board by using the SoC Builder tool.



AXI4-Stream IIO Write (HOST)Write arrays to DDR memory buffer of IP core device from simulation model
AXI4-Stream IIO Read (HOST)Read DDR memory buffer from IP core device into simulation model
AXI4-Register IIO Read (HOST)Read memory-mapped registers into simulation model
AXI4-Register IIO Write (HOST)Write data to memory-mapped registers from a simulation model
ADC To VectorConvert concatenated 16-bit ADC input samples to vector outputs
Vector To DACConvert vector inputs to concatenated 16-bit DAC output samples


SoC Model CreatorCreate SoC model based on selected reference design


soc.RFDataConverterConfigure the RF Data Converter on the RFSoC device from MATLAB