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Hardware Implementation Pane

Hardware Implementation Pane Overview

TI Delfino F2837xD configuration panel for top level model.

TI Delfino F2837xD configuration panel for CPU1.

Hardware board settings

ParameterDescriptionDefault Value
Processing UnitProcessor or CLA for model block in the MCU model.None

Design Mapping

ParameterDescriptionDefault Value
Design Mapping

Open the hardware mapping tool.

not applicable

Task profiling in simulation

ParameterDescriptionDefault Value
Show in SDI

Show the task execution data collected in simulation in the Simulation Data Inspector application.

on
Save to file

Save the task execution data to a file.

on
Overwrite file

Overwrite the last task execution data file.

off

Task profiling on processor

ParameterDescriptionDefault Value
Show in SDIShow the task execution data collected on hardware in the Simulation Data Inspector application.off
Save to fileSave the task execution data to a file.off
Overwrite fileOverwrite the last task execution data file.off
InstrumentationChoose to perform code instrumentation or Kernel instrumentation.Code
Profiling durationChoose whether to perform Kernel profiling for an unlimited or limited time duration.Unlimited

Task and memory simulation

ParameterDescriptionDefault Value
Set seed for simulating task duration and memory accessSet the random number generator seed.off
Seed ValueSpecify the seed value for the simulation of task duration deviation.

default

Cache input data at task startCache the input data at the start of a task.

off

Target hardware resources

Build Options

ParameterDescriptionDefault Value
Build action

Define how Embedded Coder® responds when you build your model.

Build, load, and run

Disable parallel build

Select to compile the generated code and driver source codes in parallel order for faster build and deployment speed.

off
Device name

Select your device from the selected processor family.

 
Enable TMUEnables support for Trigonometric Math Unit (TMU).

enabled

Boot From Flash (stand alone execution)

Specify if the application loads to the flash memory.

enabled

Use custom linker command file

Indicates that the custom linker command file must be used during the build action.

off

Linker command file

The path to the memory description file required during linking.

 
CCS hardware configuration file

The Code Composer Studio™ file required for downloading the application on the hardware.

 

Clocking - c28xCPU1

ParameterDescriptionDefault Value
Desired CPU Clock in MHzSpecify the desired CPU clock frequency (CLKIN). 
Use internal oscillatorUse the internal zero pin oscillator on the CPU.

enabled

Oscillator clock (OSCCLK) frequency in MHzOscillator frequency used in the processor.

10

Auto set PLL based on OSCCLK and CPU clockPLL values in PLLCR, DIVSEL, and Achievable SYSCLKOUT in MHz are automatically calculated based on the CPU clock entered on the board.

enabled

System PLL multiplier (SYSPLLMULT) [1-127.75]If you select Auto set PLL based on OSCCLK and CPU clock, the auto-calculated control register value matches the specified CPU clock value, based on the oscillator clock frequency.

40

System clock divider (SYSDIVSEL) [1,2,4,6,8,…,124,126]If you select Auto set PLL based on OSCCLK and CPU clock, the auto-calculated control register value matches the specified CPU clock value, based on the oscillator clock frequency.

2

Achievable SYSCLKOUT in MHz = (OSCCLK×PLLCR)/DIVSELThe auto-calculated feedback value that matches the Desired C28x CPU clock in MHz value, based on the values of OSCCLK, PLLCR, and DIVSEL.

200

Low-Speed Peripheral Clock Prescaler (LSPCLK)Prescaler value used to calculate LSPCLK based on SYSCLKOUT.

SYSCLKOUT/1

Low-Speed Peripheral Clock (LSPCLK) in MHzThe LSPCLK value calculated using the SYSCLKOUT and LSPCLK Prescaler values.

200

Clocking - c28xCPU2

ParameterDescriptionDefault Value
Set the 'Achievable SYSCLKOUT in MHz = (OSCCLK*SYSPLLMULT)/SYSDIVSEL' value calculated in CPU1

Available only for CPU2 of dual C28x core processors. Value of this parameter must be same as the value of the parameter Achievable SYSCLKOUT in MHz = (OSCCLK*PLLCR)/DIVSEL (auto calculated).

200
Select the 'Low-Speed Peripheral Clock Prescaler (LSPCLK)' option used in CPU1

Available only for CPU2 of dual C28x core processors. Value of this parameter must be same as the value of the parameter Low-Speed Peripheral Clock Prescaler (LSPCLK) specified in CPU1.

SYSCLKOUT/1
Low-Speed Peripheral Clock (LSPCLK) in MHzThe LSPCLK value calculated using the SYSCLKOUT and LSPCLK Prescaler values.200

ADC_x

ParameterDescriptionDefault Value

ADC clock prescaler (ADCCLK)

The ADCCLK divider for the c2802x, c2803x, c2806x, F28M3x, F2807x, or F2837x processor.

SYSCLKOUT/5.0

ADC clock frequency in MHz

The clock frequency for ADC, which is auto generated based on the value you select in ADC clock prescaler (ADCCLK).

40

Offset

Specify the offset value.

AdcaRegs.ADCOFFTRIM.bit.OFFTRIM

ADCEXTSOC external pin

The pin to which the ADC sends the ADCEXTSOC pulse.GPIO0

ePWM

ParameterDescriptionDefault Value

EPWM clock divider (EPWMCLKDIV)

Select the ePWM clock divider.SYSCLKOUT/2

PWM#x pin assignment

Assign the GPIO pin to the PWM#x module.

 

External Mode

ParameterDescriptionDefault Value

Communication interface

Select the type of communication interface to run your model in external mode.

Serial(using XCP)

Serial port

Select the serial communication interface module.

COM1

Baudrate

Select the baudrate of the serial communication port.

460800

Logging buffer size (in bytes)

Select the COM port used by the target hardware.

10000

Verbose

Select to view the external mode execution progress and updates in the Diagnostic Viewer or in the MATLAB command window.

off