step

Capture one buffer of data from HDL IP core running on FPGA

Description

Note

Alternatively, instead of using the step object function to perform the operation defined by the System object™, you can call the System object with arguments, as if it were a function. For example, y = step(obj,x) and y = obj(x) perform equivalent operations.

dataOut = step(DC) captures live signal data from a design running on an FPGA. The FPGA must contain an HDL IP core generated from the FPGA Data Capture Component Generator app. dataOut is a structure that contains a field for each signal captured. Call the setDataTypesetDataType object function to specify the data type of each captured signal.

If at least one signal is enabled as part of the trigger condition, the HDL IP core waits for a match of the trigger condition and captures the data. If no signals are enabled as part of the trigger condition, the HDL IP core captures and returns the buffered data immediately. When you create the object, no trigger condition is set by default. Call the setTriggerConditionsetTriggerCondition and setTriggerCombinationOperatorsetTriggerCombinationOperator object functions to configure a trigger condition.

Input Arguments

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Data capture System object, specified as an hdlverifier.FPGADataReader System object. You can create this type of System object by using the FPGA Data Capture Component Generator app.

Output Arguments

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Captured data, returned as a structure containing a field for each signal captured by FPGA Data Capture. A vector of Sample depth values for each signal requested for data capture at generation time. The fields of the structure have the names you specified for the signals.

Introduced in R2017a