setTriggerComparisonOperator

System object: hdlverifier.FPGADataReader
Package: hdlverifier

Configure operator that compares individual signal values within trigger condition

Syntax

setTriggerComparisonOperator(DC,name,operator)

Description

setTriggerComparisonOperator(DC,name,operator) specifies comparison operator that compares individual signal values within the trigger condition.

Input Arguments

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Customized data capture object created using the FPGA Data Capture Component Generator app.

Name of a trigger component signal, specified as a character vector. This name must match one of the signal names configured on creation of the System object specified as DC. The signal must be configured as a possible trigger signal.

Operator to compare signals within the trigger condition, specified as one of these operators: ==, !=, <, >, <=, or >=.

The trigger condition comprises value comparisons of one or more signals. For a multibit signal, specify one of these operators: ==, !=, <, >, <=, or >=. For a Boolean signal, specify one of these operators: == or !=. For details on trigger conditions, see Triggers.