Release control of JTAG interface


release(DC) releases system resources, including control of the JTAG interface, of the specified hdlverifier.FPGADataReader System object™. Releasing the System object enables you to change its properties and input characteristics. While the System object exists and is locked, no other processes can use the JTAG cable.

Input Arguments

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Data capture System object, specified as an hdlverifier.FPGADataReader System object. You can create this type of System object by using the FPGA Data Capture Component Generator app.

Introduced in R2017a