When using PCI Express® MATLAB as AXI Master, you must first include the following two intellectual property blocks (IPs) in your Quartus® Qsys project.
PCIe MATLAB as AXI Master is an HDL IP provided by MathWorks®. This IP connects the PCI Express (PCIe) core to your application code. It also has a configuration port for accessing configuration registers. This block diagram shows the interface to the HDL IP.
The interface includes the following parts:
resetn are the clock and
reset inputs. Connect them to the AXI clock and reset.
axs_so is a 32-bit slave interface and is used for
accessing the PCIe configuration registers. Connect this interface to the
Avalon Memory Mapped master interface.
axm_pcie is a 128-bit AXI master interface. Connect
this interface to the TX slave port on the PCIe core.
axm_app is a 128-bit AXI master interface. Connect this
interface to your application logic.
After instantiating this IP in your design, open the block parameters for configuration.
Configure these parameters:
ID_WIDTH – This parameter is the ID width in bits. Its value must match the ID width of the AXI slave.
AXI_DATA_WIDTH – This parameter is the data bus
width. The IP supports 128-bit or 256-bit data. This parameter is not
identical to the data width of the
aximaster object or
the AXI Master
Read or AXI Master
Write blocks. If the data width is set to 32 bits, and the
AXI_DATA_WIDTH of your IP is set to 128 bits,
HDL Verifier™ packs four 32-bit words to transfer on the 128-bit bus.
AXI_ADDR_WIDTH – This parameter is the address bus width. The IP supports 32-bit address.
The Hard IP for PCI Express Core is a board-specific IP provided by Intel®. Use this IP for configuring and integrating the PCI Express port.
After instantiating the PCIe core HDL IP in your Quartus Qsys project, configure the PCIe core using these steps (this example is for an Arria® 10 board).
On the Physical Function 0 IDs tab, set the parameters as shown in this figure.
On the Avalon-MM Settings tab, set the parameters as shown in this figure.
On the System Settings tab, select a Hard IP mode with a bus width to match the AXI_DATA_WIDTH parameter previously set in the PCIe MATLAB as AXI Master IP block parameters. (The IP currently supports 128-bit mode).
Connect the PCIe MATLAB as AXI Master IP to the PCIe core (this example shows Arria 10 Hard IP for PCI Express).
Compile and build your FPGA project.
Insert the FPGA board into the PCI Express slot on the motherboard of the host computer.
Program the FPGA with your compiled design.
Restart the host machine.
Once the program is running on your FPGA board, you can create a MATLAB® AXI master System object. See
aximaster. To access the slave memory locations on the board, use the
writememory methods of this System