writememory

Write data to AXI4 memory-mapped slaves

Syntax

writememory(mem,addr,data)
writememory(mem,addr,data,Name,Value)


Description

writememory(mem,addr,data) writes all words specified in data starting from the address specified in addr, and incrementing the address for each word. The address, addr, must refer to an AXI slave memory location controlled by the AXI master IP on your FPGA board. The aximaster object, mem, manages the connection between MATLAB^® and the AXI master IP.

writememory(mem,addr,data,Name,Value) writes all words specified in data starting from the address specified in addr, with additional options specified by one or more Name,Value pair arguments.

Input Arguments

mem — Connection to AXI master IP on FPGA board

aximaster object

Specify an aximaster System object™ that you created and configured.

addr — Starting address for write operation

integer | hexadecimal value

Specify an integer or a hexadecimal character vector. The object casts the address to uint32 or uint64, according to the AXI master IP address-width. The address must refer to an AXI slave memory location controlled by the AXI master IP on your FPGA board.

Memory Mapping Guidelines

• If the AXI master IP address width is 32 bits, the memory is 4 bytes aligned, and addresses have 4-byte increments (0x0, 0x4, 0x8). 0x1 is an illegal address in that case and will emit an error.

• If the AXI master IP address width is 64 bits, the memory is 8 bytes aligned, and addresses have 8-byte increments (0x0, 0x8, 0x10). 0x1 or 0x4 are illegal in that case and will emit an error.

• If the AXI master IP address width is 32 bits and Burst type is set to Increment, the address is incremented by 4 bytes.

• If the AXI master IP address width is 64 bits and Burst type is set to Increment, the address is incremented by 8 bytes.

• Do not use a 64-bit AXI master for accessing 32-bit registers.

Example: 0xa4

data — Data words to write

scalar | vector

By default, the object writes the data to a contiguous address block, incrementing the address for each operation. To turn off address increment mode and write each data value to the same location, set the BurstType property to 'Fixed' .

Before sending the write request to the FPGA, the object casts the input data to uint32, int32, uint64, or int64. The type conversion follows these rules:

• If the input data is double, then the data is cast to int32 or int64, depending on the data-width of the AXI Master IP.

• If the input data is single, then the data is cast to uint32 or uint64, depending in the AXI Master IP data width.

• If the bit width of the input data type is less than the AXI Master data width, then the data is sign extended to the width of the AXI Master data width.

• If the bit width of the input data type is longer than the AXI Master data width, then the data is cast to int32, uint32, int64, uint64. It is cast to match the data width of the AXI Master IP and the signedness of the original data type.

• If the input data is a fixed-point data type, then the object writes the stored integer value of the data.

When you specify a large operation size, such as writing a block of DDR memory, the object automatically breaks the operation into multiple bursts, using the maximum supported burst size. The maximum supported burst size is 256 words.

Properties

BurstType — AXI4 burst type

'Increment' (default) | 'Fixed'

In 'Increment' mode, the AXI master writes a vector of data to contiguous memory spaces starting with the specified address. In 'Fixed' mode, the AXI master writes all data to the same address.

Examples

Access Memory on FPGA Board from MATLAB

Before you can use this object, you must have a design running on an FPGA board connected to the MATLAB host machine. The FPGA design must include an AXI master IP that is customized for your FPGA vendor. This IP is included with the support package installation. To include the IP in your project, see Access FPGA External Memory Using MATLAB as AXI Master.

Create a MATLAB AXI master object. The object connects with the FPGA board and confirms that the IP is present.

mem = aximaster('Intel')

mem = 

  aximaster with properties:

           Vendor: 'Intel'
    JTAGCableName: 'auto'

Write and read one or more addresses with one command. By default, the commands auto-increment the address for each word of data. For example, this code writes ten addresses and then reads from a single location.

writememory(mem,140,[10:19])
rd_d = readmemory(mem,140,1)

rd_d =

  uint32

   10

Now, read from ten locations.

rd_d = readmemory(mem,140,10)

rd_d =

  1×10 uint32 row vector

   10   11   12   13   14   15   16   17   18   19

Set the BurstType property to 'Fixed' to turn off the auto-increment and access the same address multiple times. For example, this code reads ten times from the same address.

rd_d = readmemory(mem,140,10,'BurstType','Fixed')

rd_d =

  1×10 uint32 row vector

   10   10   10   10   10   10   10   10   10   10

Write ten times to the same address. In this case, the final value stored in address 140 is 29.

writememory(mem,140,[20:29],'BurstType','Fixed')
rd_d = readmemory(mem,140,10)

rd_d =

  1×10 uint32 row vector

   29   11   12   13   14   15   16   17   18   19

Alternatively, specify the address as a hexadecimal string. To cast the read data to a data type other than uint32, use the OutputDataType property.

writememory(mem,0x1c,[0:4:64])
rd_d = readmemory(mem,0x1c,16,'OutputDataType',numerictype(0,6,4))

rd_d = 

  Columns 1 through 10
         0    0.2500    0.5000    0.7500    1.0000    1.2500    1.5000    1.7500    2.0000    2.2500
  Columns 11 through 16
    2.5000    2.7500    3.0000    3.2500    3.5000    3.7500

          DataTypeMode: Fixed-point: binary point scaling
            Signedness: Unsigned
            WordLength: 6
        FractionLength: 4

When you no longer need to access the board, release the JTAG connection.

release(mem)