Intel FPGA Board Support from HDL Verifier

HDL Verifier™ automates the verification of HDL code on FPGA boards by providing connections between your FPGA board and your simulations in Simulink^® or MATLAB^®.

• FPGA-in-the-loop (FIL) enables you to run a Simulink or MATLAB simulation that is synchronized with an HDL design running on an FPGA board.

• FPGA data capture is a way to observe signals from your design while the design is running on the FPGA. It captures a window of signal data from the FPGA, based on your configuration and trigger settings, and returns the data to MATLAB or Simulink.

• MATLAB AXI master provides access to live on-board memory locations from MATLAB. You must include the MATLAB AXI master IP in your FPGA design.

To use each of these features, you must have a supported FPGA board connected to your MATLAB host computer using a supported connection type, and a supported synthesis tool.

Supported Intel FPGA Boards

This support package enables FPGA-in-the-loop simulation for the boards in the table. FPGA data capture and AXI master are available on those boards that have JTAG USB Blaster I or USB Blaster II connections.

Note

AXI Master is supported over Ethernet for Intel^® Arrow^® MAX^® 10 DECA boards.

AXI Master is supported over PCI Express for Intel Arria^® 10 GX.

Device Family	Board	Ethernet (FIL)	JTAG (FIL, AXI Master, Data Capture)	PCI Express (FIL)[a]	Comments
Intel Arria II	Arria II GX FPGA Development Kit	x	x
Intel Arria V	Arria V SoC Development Kit		x
	Arria V Starter Kit	x	x
Intel Arria 10	Arria 10 SoC Development Kit	x	x
	Arria 10 GX	x	x	x	Quartus® Prime 18.0 is not recommended for Arria 10 GX over PCI Express®.
Intel Cyclone® IV	Cyclone IV GX FPGA Development Kit	x	x
	DE2-115 Development and Education Board	x	x		The Altera® DE2-115 FPGA development board has two Ethernet ports. FPGA-in-the-loop uses only Ethernet 0 port. Make sure that you connect your host computer with the Ethernet 0 port on the board via an Ethernet cable.
	BeMicro SDK	x	x
Intel Cyclone III	Cyclone III FPGA Starter Kit		x		Altera Cyclone III boards are supported with Quartus II 13.1 Note Support for Cyclone III device family will be removed in a future release.
	Cyclone III FPGA Development Kit	x	x
	Altera Nios II Embedded Evaluation Kit, Cyclone III Edition	x	x
Intel Cyclone V	Cyclone V GX FPGA Development Kit	x	x
	Cyclone V SoC Development Kit		x
	Cyclone V GT Development Kit	x	x	x
	Terasic Atlas-SoC Kit / DE0-Nano SoC Kit		x
	Arrow SoCKit Development Kit		x
Intel Cyclone 10 LP	Altera Cyclone 10 LP Evaluation Kit		x
Intel Cyclone 10 GX	Altera Cyclone 10 GX FPGA Evaluation Kit		x		Must be used with Quartus Prime Pro
Intel MAX 10	Arrow MAX 10 DECA	x	x
Intel Stratix® IV	Stratix IV GX FPGA Development Kit	x	x
Intel Stratix V	DSP Development Kit, Stratix V Edition	x	x	x
[a] FIL over PCI Express connection is supported only for 64-bit Windows® operating systems.

Related Topics

• FPGA-in-the-Loop Simulation
• FPGA-in-the-Loop Simulation Workflows
• Data Capture Workflow
• Set Up MATLAB as AXI Master