MATLAB AXI Master

Access AXI slave memory on FPGA board from MATLAB^®

Access on-board memory locations from MATLAB, using the MATLAB AXI master IP in your FPGA design, and the aximaster object. The object connects to the IP over a JTAG, Ethernet, or a PCIe interface and allows read and write commands to slave memory locations from the MATLAB command line.

Functions

`setupAXIMasterForQuartus`	Add AXI master IP path to Quartus project
`readmemory`	Read data out of AXI4 memory-mapped slaves
`writememory`	Write data to AXI4 memory-mapped slaves
`release`	Release JTAG or Ethernet cable resource

Objects

aximaster Read and write memory locations on FPGA board from MATLAB

Blocks

AXI Master Read	Read memory locations on FPGA board from Simulink
AXI Master Write	Write memory locations on FPGA board from Simulink

Topics

Set Up MATLAB as AXI Master

High-level steps for accessing memory-mapped locations on an FPGA board from MATLAB or Simulink^®.

Ethernet MATLAB as AXI Master

Integrate and configure Ethernet MATLAB as AXI Master.

PCI Express MATLAB as AXI Master

Integrate and configure MATLAB as AXI Master IP over PCI Express.

Use Simulink to Access FPGA Locations

Access memory-mapped locations on an FPGA board from Simulink.

Featured Examples

Access FPGA External Memory Using MATLAB as AXI Master

Use MATLAB as AXI Master to access external DDR memories connected to an FPGA. The FPGA design instantiates an Intel DDR memory controller for accessing the DDR memories. This memory controller provides a memory-mapped slave interface for read and write operations from the FPGA. The MATLAB as AXI Master feature provides an AXI master IP that allows MATLAB to access any memory-mapped slave IPs in the FPGA. In this example, we demonstrate how to integrate the JTAG MATLAB as AXI Master IP or Ethernet MATLAB as AXI Master IP into a Qsys design, and then read and write the DDR memory from MATLAB.

IP Core Generation Workflow Without an Embedded ARM Processor: Arrow DECA MAX 10 FPGA Evaluation Kit

Use the HDL Coder™ IP Core Generation Workflow to develop reference designs for Intel® parts without an embedded ARM® processor present, but which still utilize the HDL Coder™ generated AXI interface to control the DUT. This example uses MATLAB as AXI Master IP from HDL Verifier™ to access the HDL Coder™ generated DUT registers by enabling the reference design parameter option Insert JTAG MATLAB as AXI Master. You can then access DUT registers from MATLAB directly. Alternatively, you can use Intel Qsys (TM) JTAG to Avalon Master Bridge IP to access the FPGA registers using Tcl commands in the Qsys System Console. For Intel JTAG AXI Master, you need to create a custom reference design. The FPGA design is implemented on the Arrow DECA MAX 10 FPGA evaluation kit.

Open Script

IP Core Generation Workflow With Ethernet Based MATLAB as AXI Master: Arrow DECA MAX 10 FPGA Evaluation Kit

Uses Ethernet based MATLAB as AXI Master IP from HDL Verifier™ to access the HDL Coder™ generated registers. MATLAB as AXI Master provides access to FPGA registers from MATLAB directly. The FPGA design is implemented on the Arrow DECA MAX 10 FPGA evaluation kit.

HDL Verifier Support Package for Intel FPGA Boards Documentation

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