Target AMD RFSoC Hardware
R2026bGenerate an HDL IP core that can integrate into RFSoC devices using AMD® Vivado® Design Suite. Use reference designs for the supported RFSoC development kits, so you can generate HDL code and port mappings to I/O and AXI registers to interface with RF tiles and DDR memory, and interactively control the FPGA design from MATLAB®.
You can use SoC Blockset™ for AMD for system-level modeling of RFSoC devices, configuration of custom RFSoC-based boards, and deployment of complete SoC applications, including executables for ARM® Cortex®-A53 processors.
Categories
- RF Data Converter Configuration
Configure RF data converter on RFSoC device from MATLAB
- Data Capture
Capture data to MATLAB or Simulink from RFSoC devices
- External Memory Access
Read and write data to PL-DDR4 memory
- Polyphase Channelizer and Multi-tile Synchronization
Learn about how to use polyphase channelizer and multi-tile synchronization
Related Information
Featured Examples
Transmit Signal Waveform Using DDR4 on AMD RFSoC Device
Design and implement hardware algorithm on FPGA fabric using IP core generation workflow.
Receive Tone with DDR4 Using IP Core Generation Workflow on Xilinx RFSoC Device
Design, simulate, and deploy algorithm to write and read captured RF samples from external DDR4 memory on Xilinx® RFSoC device.
