Support for Fixed Reference Design

Create SoC model for fixed reference design, edit created model to include algorithm, simulate and/or build and deploy model on Versal^® devices

This workflow enables algorithm and system designers to generate an HDL IP core and integrate it into a fixed reference design for rapid prototyping. Create an SoC model based on the selected reference design for the supported Xilinx^® Versal devices by using the SoC Model Creator tool. Use the created model as a template to design and simulate your FPGA algorithm and processor algorithm. Then, generate a bitstream, build a software application, and program the board by using the SoC Builder tool.

Topics

Configure Versal Design Using SoC Model Creator
Customize and design an SoC model by using the SoC Model Creator tool for Versal devices.
Generate Versal Design Using SoC Builder
Generate an SoC design and run it on the Versal device using the SoC Builder tool.

Tools

SoC Model Creator

Create SoC model based on selected reference design (Since R2021b)

Featured Examples

Full Duplex Data Streaming between Software and Hardware on Versal Platform

Design a system for full duplex data streaming between hardware and software and implement it on a Xilinx® Versal® AI Core Series VCK190 Evaluation Kit using SoC Blockset™ software. In this example, you generate the HDL code for the algorithm as an IP core, integrate it in a reference design to build a system, and deploy the system to hardware.

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