What Is Design Error Detection?

Explains the design error detection analysis option.

Derived Ranges in Design Error Detection

Explains the concepts of design ranges and derived ranges with regard to design error detection.

Run a Design Error Detection Analysis

Describes the recommended workflow for detecting design errors.

Detect Integer Overflow and Division-by-Zero Errors

An example showing how to identify design errors in your model and review analysis results.

Detect Out of Bound Array Access Errors

Detect out of bound array access errors in your model before simulation.

Detect Non-Finite, NaN, and Subnormal Floating-Point Values

Detect floating-point values in your model before simulation.

Detect Data Store Access Violations

Detect data store access violations in your model.

Detect Violations of High-Integrity Systems Modeling Guidelines

Detect violations of High-Integrity Systems Modeling Guidelines in your model.

Detect Design Errors in C/C++ Custom Code

An example showing how to detect design errors in custom C/C++ code.

Parameter Constraint Values

Overview of parameter configuration for Simulink^® Design Verifier™ analysis.

Define Constraint Values for Parameters

An example of how to specify parameters as variables for analysis.

Store Parameter Constraints in MATLAB Code Files

An example of how to import and export specified parameter constraints to and from the Parameter Table.

Define Constraint Values for Parameters in MATLAB Code Files

Describes how to define parameter configurations m MATLAB^® code files.

Using Command Line Functions to Support Changing Parameters

This example shows how to use Simulink® Design Verifier™ command-line functions to generate test data that incorporates different parameter values.

Design Verifier Pane: Design Error Detection

Specify options that control how Simulink Design Verifier detects runtime errors in the models it analyzes.

Debug Integer Overflow Design Error Detection using Model Slicer

This example shows how to use Model Slicer to debug integer overflow design errors in a Simulink model.