Detect and Address Bugs
Simulink® Design Verifier™ uses formal methods to identify hard-to-find design errors in models without requiring extensive tests or simulation runs. Design errors detected include runtime errors such as integer overflow, division by zero, and violations of design assertions and logical errors that indicate operating conditions that cannot occur. You use Simulink Design Verifier to highlight blocks in a model containing design errors and blocks proven to be without them. For each block with an error, you calculate signal-range boundaries and generate a test vector that reproduces the error in simulation.
- Detect and Address Run-Time Errors
Detect design errors, generate counterexamples
- Detect and Address Logical Errors
Identify logical errors in your model by using dead logic detection