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Construct Simulation Tests by Using the Verification Manager

Simulink® Model Verification library blocks assess time-domain signals in your model, according to the specifications that you assign to the blocks. Model verification blocks return an assertion when signals fall outside the specified limit or range. During simulation, when the signal crosses the limit, the verification block can:

  • Stop the simulation and bring immediate focus to that part of the model.

  • Report the failure with a logical signal. If the simulation does not fail, the signal output is true. If the simulation fails, the signal output is false.

For reference information on individual model verification blocks, see Model Verification.

If you use a Signal Builder block to provide test signals for your model, you can enable and disable Model Verification blocks through the Verification Manager graphical interface. To open the Verification Manager, on the Signal Builder dialog box toolbar, select the Show Verification Settings icon .

Use Model Verification Block to Check for Out-of-Bounds Signal

This example uses a Check Static Lower Bound block to stop the model simulation when a signal from a Sine Wave block crosses its lower bound limit.

In the model, the Check Static Lower Bound block has a Lower bound parameter of -0.8. The assertion is disabled, so the block appears crossed out.

1. Double-click the Check Static Lower Bound block and select the Enable assertion check box. This parameter enables the assertion of the verification block. In the model, the block is no longer crossed out.

2. Run the simulation. After 1.29517 seconds, when the signal from the Sine Wave block reaches the lower bound of -0.8, the verification block stops the simulation with this diagnostic message:

  An error occurred while running the simulation and the simulation was terminated
  Caused by:
  Assertion detected in 'ex_model_verif_block_check_static_lower_errwarn/Check Static  Lower Bound' at time 1.29517

3. To verify the signal value, double-click the Scope block.

View Model Verification Blocks in Verification Manager

This model contains a Signal Builder block that feeds five test signals to Model Verification blocks. The first four signals connect directly to Check Static Upper Bound blocks.

The fifth signal connects to a subsystem that contains a Check Static Upper Bound block.

Only the assertion for the Check Static Upper Bound3 block is enabled. The other Model Verification blocks appear crossed out in the model because their assertions are disabled.

To open the Verification Manager, double-click the Signal Builder block and select the Show Verification Settings icon.

Manage Verification Blocks and Requirement Links

The Verification Manager consists of the Verification block settings pane and the Requirements pane.

The Verification block settings pane lists all Model Verification blocks in the model, grouped by subsystem. For example, in the ex_verif_mgr_test_signals model, the Verification block settings pane displays five Check Static Upper Bound blocks. Four are in the top level of the model, and one is in a subsystem.

  • To display all of the Model Verification blocks, click the Show verification block hierarchy icon .

  • To display only the blocks that are enabled for the current signal group, click the List enabled verifications icon .

You can select additional options for viewing Model Verification blocks by right-clicking in the Verification block settings pane:

  • Display > Tree format — List the blocks as they appear in the model hierarchy.

  • Display > Overridden blocks only — List only the blocks that are not enabled for all test groups.

  • Display > Active blocks only — List only the blocks that are enabled for the current signal group.

The Requirements pane lists the requirements document links for the current signal group. If you have Simulink Requirements™, you can link requirements documents to test cases and their corresponding Model Verification blocks through this pane.

  • To open or close the Requirements pane, click the Requirements display icon .

  • To link a requirements document to a test case, in the Requirements pane, right-click and select Open Outgoing Links Dialog from the context menu. In the Outgoing Links dialog box, you can browse and select a requirements document. For more information, see Link Test Cases to Requirements Documents (Simulink Requirements).

Enable and Disable Individual Model Verification Blocks

In the Verification Manager, each verification block has a status node that indicates whether its assertion is enabled or disabled. The status node also indicates whether the enabled setting applies universally or only to the current active group. This table describes the different types of status nodes and the context menu options that are available when you right-click a node.

Node

Status

Context Menu Options

Verification block is disabled for the current active group. Click to enable for the current active group.

Block enable for all groups — Enable the verification block for all test groups. The node type changes to enabled for all groups .
Block group enable — Enable the verification block for the current active group. The node type changes to enabled .

Verification block is enabled for the current active group. Click to disable for the current active group.

Block enable for all groups — Enable the verification block for all test groups. The node type changes to enabled for all groups .
Block group disable — Disable the verification block for the current active group. The node type changes to disabled .

Verification block is enabled for all test groups.

Block enable by group — Restore the individually enabled/disabled settings to this block for all test groups. Depending on your previous selection, the node type changes to enabled or disabled

When you use the Verification Manager to enable a model verification block for the current active group, in the model, the block displays an Override label. For example, in the ex_verif_mgr_test_signals model, when you select Group 2 from the Active Group list, the Verification Manager shows that the Check Static Upper Bound1 block is enabled.

In the model, the Check Static Upper Bound1 block is not crossed out, but displays an Override label.

Enable and Disable Model Verification Blocks by Subsystem

If your model contains many verification blocks, it is tedious to enable and disable blocks individually. Using the Verification Manager, you can enable and disable all blocks in a subsystem. In the Verification block settings pane, right-click the subsystem node and select from these context menu options:

  • Contents enable for all groups — Enable all verification blocks in this subsystem for all test groups.

  • Contents enable by group — Restore the individually enabled/disabled settings to each verification block in this subsystem for all test groups.

  • Contents group enable — Individually enable all verification blocks in this subsystem for the current active group.

  • Contents group disable — Individually disable all verification blocks in this subsystem for the current active group.

For example, in the ex_verif_mgr_test_signals model, you can enable all of the verification blocks for all test groups by double-clicking the ex_verif_mgr_test_signals node and selecting Contents enable for all groups. In the Verification Manager, all nodes change to enabled for all groups .

To restore the individually enabled/disabled settings for each verification block in each group, double-click the ex_verif_mgr_test_signals node and select Contents enable by group.

Linear System Modeling Blocks in Simulink Control Design

If you have Simulink Control Design™, you can:

  • Monitor time-domain and frequency-domain characteristics.

  • Specify bounds on linear system characteristics.

  • Check that the bounds are satisfied during simulation.

For reference information on individual blocks, see Model Verification (Simulink Control Design).

See Also

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