# SPICE PMOS

SPICE-compatible P-Channel MOSFET

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• Simscape / Electrical / Additional Components / SPICE Semiconductors

## Description

The SPICE PMOS block represents a SPICE-compatible positive-channel (P-Channel) metal-oxide semiconductor (MOS) field-effect transistor (FET). If the gate-source voltage decreases, the channel conductance increases. If the gate-source voltage is increased, the channel conductance decreases.

SPICE, or Simulation Program with Integrated Circuit Emphasis, is a simulation tool for electronic circuits. You can convert some SPICE subcircuits into equivalent Simscape™ Electrical™ models using the Environment Parameters block and SPICE-compatible blocks from the Additional Components library. For more information, see subcircuit2ssc.

### Equation Variables

Variables for the SPICE PMOS block equations include:

• Variables that you define by specifying parameters for the SPICE PMOS block. The visibility of some of the parameters depends on the value that you set for other parameters. For more information, see Parameters.

• Geometry-adjusted variables, which depend on several of the values that you specify using parameters for the SPICE PMOS block. For more information, see Geometry-Adjusted Variables.

• Temperature, T, which is 300.15 K by default. You can use a different value by specifying parameters for the SPICE PMOS block or by specifying parameters for both the SPICE PMOS block and an Environment Parameters block. For more information, see Transistor Temperature.

• Minimal conductance, GMIN, which is 1e-12 1/Ohm by default. You can use a different value by specifying a parameter for an Environment Parameters block. For more information, see Minimal Conduction.

Several variables in the equations for the SPICE P-channel MOSFET model consider the geometry of the device that the block represents. These geometry-adjusted variables depend on variables that you define by specifying SPICE PMOS block parameters. The geometry-adjusted variables depend on these variables:

• AREA — Area of the device

• SCALE — Number of parallel connected devices

The table includes the geometry-adjusted variables and the defining equations.

VariableDescriptionEquation

$K{P}_{d}=KP*AREA*SCALE$

$I{S}_{d}=IS*AREA*SCALE$

JSdGeometry-adjusted bulk junction saturation current density

$J{S}_{d}=JS*AREA*SCALE$

$CB{D}_{d}=CBD*AREA*SCALE$

$CB{S}_{d}=CBS*AREA*SCALE$

$CGS{O}_{d}=CGSO*AREA*SCALE$

$CGD{O}_{d}=CGDO*AREA*SCALE$

$CGB{O}_{d}=CGBO*AREA*SCALE$

CJGeometry-adjusted bottom capacitance per junction area

$C{J}_{d}=CJ*AREA*SCALE$

CJSWGeometry-adjusted sidewall capacitance per junction perimeter

$CJS{W}_{d}=CJSW*AREA*SCALE$

$R{D}_{d}=\frac{RD}{AREA*SCALE}$

$R{S}_{d}=\frac{RS}{AREA*SCALE}$

$RS{H}_{d}=\frac{RSH}{AREA*SCALE}$

Transistor Temperature

There are two different options for defining transistor temperature, T:

• Fixed temperature — The block uses a temperature that is independent of the circuit temperature when the Model temperature dependence using parameter in the Temperature settings of the SPICE PMOS block is set to Fixed temperature. For this model, the block sets T equal to TFIXED.

• Device temperature — The block uses a temperature that depends on circuit temperature when the Model temperature dependence using parameter in the Temperature settings of the SPICE PMOS block is set to Device temperature. For this model, the block defines temperature as

$T={T}_{C}+TOFFSET$

Where:

• TC is the circuit temperature.

If there is not an Environment Parameters block in the circuit, TC is equal to 300.15 K.

If there is an Environment Parameters block in the circuit, TC is equal to the value that you specify for the Temperature parameter in the SPICE settings of the Environment Parameters block. The default value for the Temperature parameter is 300.15 K.

• TOFFSET is the offset local circuit temperature.

Minimal Conduction

Minimal conductance, GMIN, has a default value of 1e–12 1/Ohm. To specify a different value:

1. If there is not already an Environment Parameters block in the circuit, add one.

2. In the SPICE settings of the Environment Parameters block, specify the desired GMIN value for the GMIN parameter.

Thermal Voltage

Vtn is the thermal voltage, which is defined as

${V}_{tn}=N\frac{k*T}{q}$

Where:

• N is the emission coefficient.

• T is the transistor temperature. For more information, see Transistor Temperature.

• k is the Boltzmann constant.

• q is the elementary charge on an electron.

### Parameters Calculations

The tables show how the SPICE PMOS block determines some of its parameters based on values that you specify.

Drain Resistance

Drain resistance, RDSheet resistance, RSHNumber of drain squares, NRD
NaNNaNNaN0
NaNRSHNaN0
NaNNaNNRD0
RDNaN or RSHNaN or NRDRDd
NaNRSHNRDRSHd*NRD

Source Resistance

Source resistance, RSSheet resistance, RSHNumber of source squares, NRS
NaNNaNNaN0
NaNRSHNaN0
NaNNaNNRS0
RSNaN or RSHNaN or NRSRSd
NaNRSHNRSRSHd*NRS

Transconductance and Surface Mobility

Parameter ValuesGeometry-Adjusted Transconductance (level 1), in A/V2Geometry-Adjusted Transconductance (level 3), in A/V2Surface mobility (level 3), in cm2/s/V
Oxide thickness, TOXSurface mobility, U0Transconductance, KP
NaNNaNNaN2e-5 (default value)2e-5 (default value)600 (default value)
NaNNaNKPKPdKPd600
NaNU0NaN2e-5UO*EPXox/1e-7U0
NaNU0KPKPdKPdU0
TOXNaNNaN600*EPXox/TOX600*EPXox/TOX600
TOXNaNKPKPdKPd600
TOXU0NaNUO*EPXox/TOXUO*EPXox/TOXU0
TOXU0KPKPdKPdU0

Oxide Thickness and Threshold Voltage

Parameter ValuesSurface potential, PHI (level 1), in VThreshold voltage, VTO (level 1), in VSurface potential, PHI (level 3), in VThreshold voltage, VTO (level 3), in V
Oxide thickness, TOXSubstrate doping, NSUBSurface potential, PHIThreshold voltage, VTO
NaNNaNNaNNaN0.6 (default value)0 (default value)0.6 (default value)0 (default value)
NaNNaNNaNVTO0.6VTO0.6VTO
NaNNaNPHINaNPHI0PHI0
NaNNaNPHIVTOPHIVTOPHIVTO
NaNNSUBNaNNaN0.60PHI (1e-7, NSUB)VTO (1e-7, NSUB)
NaNNSUBNaNVTO0.6VTOPHI (1e-7, NSUB)VTO
NaNNSUBPHINaNPHI0PHIVTO (1e-7, NSUB)
NaNNSUBPHIVTOPHIVTOPHIVTO
TOXNaNNaNNaN0.600.60
TOXNaNNaNVTO0.6VTO0.6VTO
TOXNaNPHINaNPHI0PHI0
TOXNaNPHIVTOPHIVTOPHIVTO
TOXNSUBNaNNaNPHI (NSUB, TOX)VTO (NSUB, TOX)PHI (NSUB, TOX)VTO (NSUB, TOX)
TOXNSUBNaNVTOPHI (NSUB, TOX)VTOPHI (NSUB, TOX)VTO
TOXNSUBPHINaNPHIVTO (NSUB, TOX)PHIVTO (NSUB, TOX)
TOXNSUBPHIVTOPHIVTOPHIVTO

Where PHI (NSUB, TOX), PHI (1e-7, NSUB), VTO (NSUB, TOX), and VTO (1e-7, NSUB) are obtained using these equations:

$PHI=2\frac{kT}{q}\mathrm{ln}\left(\frac{NSUB}{ni}\right)$

$GAMMA=\frac{\sqrt{2q{\epsilon }_{si}NSUB}}{{C}_{ox}}$

$\begin{array}{l}{V}_{FB}={\phi }_{MS}-\frac{qNSS}{{C}_{ox}}\\ {V}_{{T}_{O}}={V}_{FB}-PHI-GAMMA*\sqrt{PHI}.\end{array}$

### Bulk-Source Diode Model

The table shows the equations that define the relationship between the source-bulk current, Isb, and voltage, Vsb. As applicable, the model parameters are first adjusted for temperature. For more information, see Temperature Dependence.

Applicable Range of Vsb ValuesCorresponding Igs Equation

${V}_{sb}>80*{V}_{tn}$

${I}_{sb}=I{S}_{sb}*\left(\left(\frac{{V}_{sb}}{{V}_{tn}}-79\right){e}^{80}-1\right)+{V}_{sb}*G\mathrm{min}$

$80{V}_{tn}\ge {V}_{sb}$

${I}_{sb}=I{S}_{sb}*\left({e}^{{V}_{sb}/{V}_{tn}}-1\right)+{V}_{sb}*G\mathrm{min}$

Where:

• ISsb is the bulk saturation current, such that, if:

• $J{S}_{d}\ne 0$ and $AS\ne 0$, $I{S}_{sb}=J{S}_{d}*AS$.

Where:

• JSd is the geometry-adjusted bulk junction saturation current density.

• AS is the source area.

• If $J{S}_{d}=0$ or $AS=0$, $I{S}_{sb}=I{S}_{d}$, where ISd is the geometry-adjusted bulk saturation current.

• Vtn is the thermal voltage. For more information, see Thermal Voltage.

• Gmin is the minimal conductance. For more information, see Minimal Conduction.

### Bulk-Drain Diode Model

The table shows the equations that define the relationship between the drain-bulk current, Idb, and voltage, Vdb. As applicable, the model parameters are first adjusted for temperature. For more information, see Temperature Dependence.

Applicable Range of Vdb ValuesCorresponding Idb Equation

${V}_{db}>80*{V}_{tn}$

${I}_{db}=I{S}_{db}*\left(\left(\frac{{V}_{db}}{{V}_{tn}}-79\right){e}^{80}-1\right)+{V}_{db}*G\mathrm{min}$

$80{V}_{tn}\ge {V}_{db}$

${I}_{db}=I{S}_{db}*\left({e}^{{V}_{db}/{V}_{tn}}-1\right)+{V}_{db}*G\mathrm{min}$

Where:

• ISdb is the bulk drain current, such that:

• If $J{S}_{d}\ne 0$ and $AD\ne 0$, $I{S}_{db}=J{S}_{d}*AD$.

Where:

• JSd is the geometry-adjusted bulk junction saturation current density.

• AD is the drain area.

• If $J{S}_{d}=0$ or $AD=0$, $I{S}_{db}=I{S}_{d}$, where ISd is the geometry-adjusted bulk saturation current.

• Vtn is the thermal voltage. For more information, see Thermal Voltage.

• Gmin is the minimal conductance. For more information, see Minimal Conduction.

### Level 1 Drain Current Model

This table shows relationship between the drain current Isd and the source-drain voltage Vsd in normal mode (Vsd ≥ 0). As applicable, model parameters are first adjusted for temperature.

Normal Mode

Applicable Range of Vsg and Vsd ValuesCorresponding Isd Equation

${V}_{sg}-{V}_{on}\le 0$

${I}_{sd}=0$

$0<{V}_{sg}-{V}_{on}\le {V}_{sd}$

${I}_{sd}=BETA*{\left({V}_{sg}-{V}_{on}\right)}^{2}\frac{\left(1+LAMBDA*{V}_{sd}\right)}{2}$

$0<{V}_{sd}<{V}_{sg}-{V}_{on}$

$\begin{array}{c}{I}_{sd}=BETA*\\ {V}_{sd}\left(\left({V}_{sg}-{V}_{on}\right)-\frac{{V}_{sd}}{2}\right)\left(1+LAMBDA*{V}_{sd}\right)\end{array}$

Where:

• Von depends on Vsb and PHI.

Applicable Relationship of Vsb and PHI ValuesCorresponding Von Equation

${V}_{sb}\le 0$

${V}_{on}=MTYPE*VBI+GAMMA\sqrt{PHI-{V}_{sb}}$

$0<{V}_{sb}\le 2*PHI$

${V}_{on}=MTYPE*VBI+GAMMA\left(\sqrt{PHI}-\frac{{V}_{sb}}{2\sqrt{PHI}}\right)$

${V}_{sb}>2*PHI$

${V}_{on}=MTYPE*VBI$

• MTYPE is -1.

• BETA is $BETA=\left(K{P}_{d}*WIDTH\right)/\left(LENGTH-2*LD\right)$

• KP is:

• The Transconductance, KP, if this parameter has a numerical value.

• $U0*3.9*{\epsilon }_{0}/TOX$, if Transconductance, KP is NaN and you specify values for both the Oxide thickness, TOX and Substrate doping, NSUB parameters.

• WIDTH is the channel width.

• LENGTH is the channel length.

• LD is the lateral diffusion.

• VBI is a built-in voltage value the block uses in calculations. The value is a function of temperature. For a detailed definition, see Temperature Dependence.

• PHI is:

• The Surface potential, PHI, if this parameter has a numerical value.

• $2*k{T}_{meas}/q*\mathrm{log}\left(NSUB/{n}_{i}\right)$, if Surface potential, PHI is NaN and you specify values for both the Oxide thickness, TOX and Substrate doping, NSUB parameters.

• LAMBDA is the channel modulation.

• GAMMA is:

• The Bulk threshold, GAMMA, if this parameter has a numerical value.

• $TOX*\sqrt{2*11.7*{\epsilon }_{0}*q*NSUB}/\left(3.9*{\epsilon }_{0}\right)$, if Bulk threshold, GAMMA is NaN and you specify values for both the Oxide thickness, TOX and Substrate doping, NSUB parameters.

• ε0 is the permittivity of free space, 8.854214871e-12 F/m.

• ni is the carrier concentration of intrinsic silicon, 1.45e10 cm-3.

This table shows relationship between the drain current Isd and the source-drain voltage Vsd in inverse mode (Vsd < 0). As applicable, model parameters are first adjusted for temperature.

Inverse Mode

Applicable Range of Vdg and Vsd ValuesCorresponding Isd Equation

${V}_{dg}-{V}_{on}\le 0$

${I}_{sd}=0$

$0<{V}_{dg}-{V}_{on}\le -{V}_{sd}$

${I}_{sd}=-BETA{\left({V}_{dg}-{V}_{on}\right)}^{2}\left(1-LAMBDA*{V}_{sd}\right)/2$

$0<-{V}_{sd}<{V}_{dg}-{V}_{on}$

$\begin{array}{c}{I}_{sd}=BETA*\\ {V}_{sd}\left(\left({V}_{dg}-{V}_{on}\right)+{V}_{sd}/2\right)\left(1-LAMBDA*{V}_{sd}\right)\end{array}$

Von depends on Vdb and PHI.

Applicable Relationship of Vdb and PHI ValuesCorresponding Von Equation

${V}_{db}\le 0$

${V}_{on}=MTYPE*VBI+GAMMA\sqrt{PHI-{V}_{db}}$

$0<{V}_{db}\le 2*PHI$

${V}_{on}=MTYPE*VBI+GAMMA\left(\sqrt{PHI}-\frac{{V}_{db}}{2\sqrt{PHI}}\right)$

${V}_{db}>2*PHI$

${V}_{on}=MTYPE*PHI$

### Level 3 Drain Current Model

The block provides the following model for drain current Isd in normal mode (${V}_{sd}\ge 0$) after adjusting the applicable model parameters for temperature.

${I}_{SD}={I}_{SD0}*Scal{e}_{VMAX}*Scal{e}_{LChan}*Scal{e}_{INV}$

Where:

The block uses the same model for drain current in inverse mode (${V}_{sd}<0$), with the following substitutions:

• ${V}_{sb}\equiv {V}_{sb}-{V}_{sd}$

• ${V}_{sg}\equiv {V}_{sg}-{V}_{sd}$

• ${V}_{sd}\equiv -{V}_{sd}$

Basic Drain Current Model

The relationship between the drain current Isd and the source-drain voltage Vsd is

${I}_{SD0}=BETA*{F}_{gate}*\left({V}_{SGX}-{V}_{TH}-\frac{1+{F}_{B}}{2}*{V}_{SDX}\right)*{V}_{SDX}$

Where:

• BETA is calculated as described in Level 1 Drain Current Model.

• FGATE is calculated as

${F}_{gate}=\frac{1}{1+THETA*\left({V}_{sgx}-{V}_{TH}\right)}$

Where:

• THETA models the dependence of the mobility on the gate-source voltage.

• ${V}_{sgx}=\mathrm{max}\left({V}_{SG},{V}_{on}\right)$

• If you specify a nonzero value for the Fast surface state density, NFS parameter, the block calculates Von using this equation:

${V}_{on}={V}_{TH}+{x}_{n}{V}_{T}$

Otherwise,

${V}_{on}={V}_{TH}$

• The block calculates xn as

${x}_{n}=1+\frac{q*NFS}{COX}+\frac{\left(GAMMA*{F}_{s}*\sqrt{{V}_{bulk}}+\frac{{F}_{n}*{V}_{bulk}}{WIDTH}\right)}{2*{V}_{bulk}}$

• The block calculates Vbulk as follows:

• If

${V}_{SB}\le 0,$

${V}_{bulk}=PHI-{V}_{SB}.$

• Otherwise, the block calculates Vbulk as

${V}_{bulk}=\frac{PHI}{{\left(1+\frac{{V}_{SB}}{2*PHI}\right)}^{2}}$

• Thermal voltage such that

${V}_{T}=\frac{kT}{q}$

• The block calculates VTH using the following equation:

$\begin{array}{l}{V}_{TH}={V}_{BI}-\frac{8.15{e}^{-22}*ETA}{COX*{\left(LENGTH-2*LD\right)}^{3}}*{V}_{SD}\\ \text{​}\text{​}\text{​}\text{​}\text{​}\text{​}\text{​}\text{​}\text{​}\text{​}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}+GAMMA*{F}_{s}*\sqrt{{V}_{bulk}}+{F}_{n}*{V}_{bulk}\end{array}$

• For information about how the block calculates VBI, see Temperature Dependence.

• ETA is the Vds dependence threshold volt, ETA.

• $COX=\frac{{\epsilon }_{ox}}{TOX},$

Where εox is the permittivity of the oxide and TOX is the Oxide thickness, TOX.

• If you specify a nonzero value for the Junction depth, XJ parameter and a value for the Substrate doping, NSUB parameter, the block calculates Fs using these equations:

$\alpha =\frac{2{\epsilon }_{si}}{qNSUB}$

$XD=\sqrt{\alpha }$

$wc=.0631353+.8013292*\frac{XD*\sqrt{{V}_{bulk}}}{XJ}-.01110777*{\left(\frac{XD*\sqrt{{V}_{bulk}}}{XJ}\right)}^{2}+\frac{LD}{XJ}$

${F}_{s}=1-\left(wc*{\sqrt{1-\left(\frac{XD*\sqrt{{V}_{bulk}}}{XJ+XD*\sqrt{{V}_{bulk}}}\right)}}^{2}-\frac{LD}{XJ}\right)$

Where εsi is the permittivity of silicon.

Otherwise,

${F}_{s}=1$

• The block calculates FB as

${F}_{B}=\frac{GAMMA*{F}_{s}}{4*\sqrt{{V}_{bulk}}}+{F}_{n}$

• The block calculates Fn as

${F}_{n}=\frac{DELTA*\pi *{\epsilon }_{si}}{2*COX*WIDTH}$

• DELTA is the width effect on threshold.

• VSDX is the lesser of VSD and the saturation voltage, Vdsat.

• If you specify a positive value for the Max carrier drift velocity, VMAX parameter, the block calculates Vdsat using the following equation:

$\begin{array}{l}{V}_{dsat}=\frac{{V}_{sgx}-{V}_{TH}}{1+{F}_{B}}+\frac{\left(LENGTH-2*LD\right)*VMAX}{UO*{F}_{gate}}\\ \text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}-\sqrt{{\left(\frac{{V}_{sgx}-{V}_{TH}}{1+{F}_{B}}\right)}^{2}+{\left(\frac{\left(LENGTH-2*LD\right)*VMAX}{UO*{F}_{gate}}\right)}^{2}}\end{array}$

Otherwise, the block calculates Vdsat as

${V}_{dsat}=\frac{{V}_{sgx}-{V}_{TH}}{1+{F}_{B}}$

Velocity Saturation Scaling

If you specify a positive value for the Max carrier drift velocity, VMAX parameter, the block calculates ScaleVMAX as

$Scal{e}_{VMAX}=\frac{1}{1+\frac{UO*{F}_{gate}}{\left(LENGTH-2*LD\right)*VMAX}*{V}_{SDX}}$

Otherwise,

$Scal{e}_{VMAX}=1$

Channel Length Modulation Scaling

The block scales the drain current to account for channel length modulation if ${V}_{SD}>V{}_{dsat}$ and the Max carrier drift velocity, VMAX is less than or equal to zero or α is nonzero.

The block scales the drain current using the following equation:

$Scal{e}_{LChan}=\frac{1}{1-\frac{\Delta l}{\left(LENGTH-2*LD\right)}}$

To calculate $\Delta l$ the block:

1. Calculates the intermediate value $\Delta {l}_{\text{0}}$.

• If you specify a positive value for the Max carrier drift velocity, VMAX parameter, the block computes the intermediate value gdsat as the greater of 1e-12 and the result of the following equation:

${I}_{SD0}*\left(1-\frac{1}{1+Scal{e}_{{g}_{dsat}}*{V}_{SDX}}\right)*Scal{e}_{{g}_{dsat}}$

Where:

$Scal{e}_{{g}_{dsat}}=\frac{UO*{F}_{gate}}{\left(LENGTH-2*LD\right)*VMAX}$

Then, the block uses the following equation to calculate the intermediate value Δl0:

$\begin{array}{l}\Delta {l}_{0}=\sqrt{{\left(\frac{KA*{I}_{SD}}{2*\left(LENGTH-2*LD\right)*{g}_{dsat}}\right)}^{2}+KA*\left({V}_{SD}-{V}_{dsat}\right)}\\ \text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}-\frac{KA*{I}_{SD}}{2*\left(LENGTH-2*LD\right)*{g}_{dsat}}\end{array}$

Where

$KA=KAPPA*\alpha .$

• Otherwise, the block uses the following equation to calculate the intermediate value $\Delta {l}_{\text{0}}$ as

$\Delta l=\sqrt{KA*\left({V}_{SD}-{V}_{dsat}\right)}$

2. The block checks for punch through and calculates $\Delta l$.

• If

$\Delta {l}_{\text{0}}>\left(LENGTH-2*LD\right)/2,$

the block calculates $\Delta l$ using the following equation:

$\Delta l=\left(1-\frac{\left(LENGTH-2*LD\right)}{4*\Delta {l}_{0}}\right)*\left(LENGTH-2*LD\right)$

• Otherwise,

$\Delta l=\Delta {l}_{0}.$

Weak Inversion Scaling

If VSG is less than Von, the block calculates ScaleINV using the following equation:

$Scal{e}_{INV}={e}^{\frac{{V}_{sg}-{V}_{on}}{{x}_{n}*{V}_{T}}}$

Otherwise,

$Scal{e}_{INV}=1$

### Junction Charge Model

The block models the Junction Overlap Charges and the Bulk Junction Charges.

Junction Overlap Charges

The block calculates the following junction overlap charges:

• ${Q}_{SG}=CGS{O}_{d}*WIDTH*{V}_{sg}$

Where:

• QSG is the source-gate overlap charge.

• CGSOd is the geometry adjusted gate-source overlap capacitance.

• WIDTH is the channel width.

• ${Q}_{DG}=CGD{O}_{d}*WIDTH*{V}_{dg}$

Where:

• QDG is the drain-gate overlap charge.

• CGDOd is the geometry adjusted gate-drain overlap capacitance.

• ${Q}_{BG}=CGB{O}_{d}*\left(LENGTH-2*LD\right)*{V}_{bg}$

Where:

• QBG is the bulk-gate overlap charge.

• CGBOd is the geometry adjusted gate-bulk overlap capacitance.

• LENGTH is the channel length.

• LD is the lateral diffusion.

Bulk Junction Charges

This table shows relationship between the bulk-drain bottom junction charge Qbottom and the junction voltage, Vdb. As applicable, model parameters are first adjusted for temperature.

Applicable Range of Vdb ValuesCorresponding Qbottom Equation
${V}_{db}

${Q}_{bottom}=\frac{CB{D}_{d}*PB*\left(1-{\left(1-\frac{{V}_{db}}{PB}\right)}^{1-MJ}\right)}{1-MJ}$ if CBD > 0.

${Q}_{bottom}=\frac{C{J}_{d}*AD*PB*\left(1-{\left(1-\frac{{V}_{db}}{PB}\right)}^{1-MJ}\right)}{1-MJ}$ otherwise.

${V}_{db}\ge FC*PB$

$\begin{array}{l}{Q}_{bottom}=CB{D}_{d}*\\ \text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\left(F1+\frac{F3*\left({V}_{db}-FC*PB\right)+\frac{MJ*\left({V}_{db}^{2}-{\left(FC*PB\right)}^{2}\right)}{2*PB}}{F2}\right)\end{array}$ if $CB{D}_{d}>0$.

$\begin{array}{l}{Q}_{bottom}=C{J}_{d}*AD*\\ \text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\left(F1+\frac{F3*\left({V}_{db}-FC*PB\right)+\frac{MJ*\left({V}_{db}^{2}-{\left(FC*PB\right)}^{2}\right)}{2*PB}}{F2}\right)\end{array}$

otherwise.

Where:

• PB is the bulk junction potential.

• FC is the capacitance coefficient.

• CBDd is the geometry-adjusted zero-bias bulk-drain capacitance.

• CJd is the geometry-adjusted bottom capacitance per junction area.

• AD is the drain area.

• MJ is the bottom grading coefficient.

• $F1=\frac{PB*\left(1-{\left(1-FC\right)}^{1-MJ}\right)}{1-MJ}$

• $F2={\left(1-FC\right)}^{1+MJ}$

• $F3=1-FC*\left(1+MJ\right)$

To calculate the bulk-source bottom junction charge, the block substitutes variables in the equations in the preceding table. The block substitutes:

• Vsb replaces Vdb.

• CBSd for CBDd

This table shows relationship between the bulk-drain sidewall junction charge Qsidewall and the junction voltage Vdb. As applicable, model parameters are first adjusted for temperature.

Applicable Range of Vdb ValuesCorresponding Qsidewall Equation
${V}_{db}${Q}_{sidewall}=\frac{CJS{W}_{d}*PD*PB*\left(1-{\left(1-\frac{{V}_{db}}{PB}\right)}^{1-MJSW}\right)}{1-MJSW}$
${V}_{db}\ge FC*PB$$\begin{array}{l}{Q}_{sidewall}=CJS{W}_{d}*PD*\\ \text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\left(F1+\frac{F3*\left({V}_{db}-FC*PB\right)+\frac{MJSW*\left({V}_{db}^{2}-{\left(FC*PB\right)}^{2}\right)}{2*PB}}{F2}\right)\end{array}$

Where:

• CJSWd is the geometry adjusted sidewall capacitance per junction perimeter.

• PD is the drain perimeter.

• MGSW is the side grading coefficient.

• $F1=\frac{PB*\left(1-{\left(1-FC\right)}^{1-MJSW}\right)}{1-MJSW}$

• $F2={\left(1-FC\right)}^{1+MJSW}$

• $F3=1-FC*\left(1+MJSW\right)$

To calculate the bulk-source sidewall junction charge and the sidewall junction voltage, the block substitutes variables in the equations in the preceding table. The block substitutes:

• Vsb replaces Vdb.

• PS for PD

### Capacitance Model

The SPICE PMOS block allows you to model the transistor capacitance model in three different ways:

• No intrinsic capacitance model

Meyer Gate Capacitance Model

This table shows the relationship between the operational regions of the transistor and the gate-bulk, gate-drain, and gate-source capacitances.

Operational regionGate-Bulk, Cgb, Gate-Drain, Cgd, and Gate-Source, Cgs, Equations
Accumulation region, ${V}_{gb}<{V}_{FB}$$\begin{array}{l}{C}_{gb}=Coxt\\ {C}_{gd}=0\\ {C}_{gs}=0\end{array}$
Depletion region, ${V}_{gs}<{V}_{TH}$$\begin{array}{l}{C}_{gb}=\frac{Coxt}{\sqrt{1+\frac{4}{GAMM{A}^{2}}*\left({V}_{gb}-{V}_{FB}\right)}}\\ {C}_{gd}=0\\ {C}_{gs}=0\end{array}$
Saturation region, ${V}_{gs}-{V}_{TH}<{V}_{ds}$if ${V}_{ds}<{V}_{satmin}$ then:if ${V}_{ds}\ge {V}_{satmin}$ then:
$\begin{array}{l}{C}_{gb}=0\\ {C}_{gd}=\frac{2}{3}\left(Coxt-{C}_{gb}\right)\left(1-\frac{{\left({V}_{satmin}\right)}^{2}}{{\left(2{V}_{satmin}-{V}_{ds}\right)}^{2}}\right)\\ {C}_{gs}=\frac{2}{3}\left(Coxt-{C}_{gb}\right)\left(1-\frac{{\left({V}_{satmin}-{V}_{ds}\right)}^{2}}{{\left(2{V}_{satmin}-{V}_{ds}\right)}^{2}}\right)\end{array}$$\begin{array}{l}{C}_{gb}=0\\ {C}_{gd}=0\\ {C}_{gs}=\frac{2}{3}\left(Coxt-{C}_{gb}\right)\end{array}$
Linear region, ${V}_{gs}-{V}_{TH}>{V}_{ds}$$\begin{array}{l}{C}_{gb}=0\\ {C}_{gd}=\frac{2}{3}\left(Coxt-{C}_{gb}\right)*\left(1-\frac{{\left({V}_{gs}-{V}_{TH}\right)}^{2}}{{\left(2*\left({V}_{gs}-{V}_{TH}\right)-{V}_{ds}\right)}^{2}}\right)\\ {C}_{gs}=\frac{2}{3}\left(Coxt-{C}_{gb}\right)*\left(1-\frac{{\left({V}_{gs}-{V}_{TH}-{V}_{ds}\right)}^{2}}{{\left(2*\left({V}_{gs}-{V}_{TH}\right)-{V}_{ds}\right)}^{2}}\right)\end{array}$

where:

• $Coxt=WIDTH*\left(LENGTH-2*LD\right)*COX*AREA*SCALE$

• ${V}_{FB}=VBI*MTYPE-PHI$ is the flat-band voltage.

• Vsatmin is the minimum saturation voltage. It is a predefined parameter equal to 1 V.

These equations are continuous between the depletion region and the accumulation region, and discontinuous between the depletion and the inversion region. Other SPICE tools apply smoothing functions between the inversion and depletion regions.

$\begin{array}{l}{C}_{gb}=\frac{WIDTH*LENGTH*COX}{\sqrt{{\left(1+\frac{4}{GAMM{A}^{2}}*\left({V}_{TH}-{V}_{bs}-{V}_{FB}\right)\right)}^{m}}}*smoothing\\ smoothing=\frac{1}{{\left(1+\frac{4}{GAMM{A}^{2}}*\left({V}_{gs}-{V}_{TH}\right)\right)}^{m}}\end{array}$

where m is a predefined smoothing constant.

Charge Conservation Capacitance Model

This table shows the relationship between the operational regions of the transistor and the gate, bulk, channel, drain, and source charges for a level 1 MOS.

Operational regionLevel-1 Charges Equations
Accumulation region, ${V}_{gb}<{V}_{FB}$$\begin{array}{l}{Q}_{g}=Coxt*\left({V}_{gb}-{V}_{FB}\right)\\ {Q}_{b}=-Coxt*\left({V}_{gb}-{V}_{FB}\right)\\ {Q}_{c}=0\\ {Q}_{d}=0\\ {Q}_{s}={Q}_{c}-{Q}_{d}\end{array}$
Depletion region, ${V}_{gs}<{V}_{TH}$$\begin{array}{l}{Q}_{g}=-0.5*Coxt*GAMM{A}^{2}*\left(1-\sqrt{1+\frac{4}{GAMM{A}^{2}}*\left({V}_{gb}-{V}_{FB}\right)}\right)\\ {Q}_{b}=0.5*Coxt*GAMM{A}^{2}*\left(1-\sqrt{1+\frac{4}{GAMM{A}^{2}}*\left({V}_{gb}-{V}_{FB}\right)}\right)\\ {Q}_{c}=0\\ {Q}_{d}=0\\ {Q}_{s}={Q}_{c}-{Q}_{d}\end{array}$
Saturation region, ${V}_{gs}-{V}_{TH}<{V}_{ds}$$\begin{array}{l}{Q}_{g}=Coxt*\left({V}_{gs}-{V}_{FB}-PHI-\frac{{V}_{gs}-{V}_{TH}}{3}\right)\\ {Q}_{b}=-Coxt*\left({V}_{TH}-{V}_{FB}-PHI\right)\\ {Q}_{c}=-Coxt*\left({V}_{gs}-{V}_{TH}-\frac{{V}_{gs}-{V}_{TH}}{3}\right)\\ {Q}_{d}=0\\ {Q}_{s}={Q}_{c}-{Q}_{d}\end{array}$
Linear region, ${V}_{gs}-{V}_{TH}>{V}_{ds}$$\begin{array}{l}{Q}_{g}=Coxt*\left({V}_{gs}-{V}_{FB}-PHI-\frac{{V}_{ds}}{2}+\frac{{V}_{ds}{}^{2}}{12\left({V}_{gs}-{V}_{TH}-0.5{V}_{ds}\right)}\right)\\ {Q}_{b}=-Coxt*\left({V}_{TH}-{V}_{FB}-PHI\right)\\ {Q}_{c}=-Coxt*\left({V}_{gs}-{V}_{TH}-\frac{{V}_{ds}}{2}+\frac{{V}_{ds}{}^{2}}{12\left({V}_{gs}-{V}_{TH}-0.5{V}_{ds}\right)}\right)\\ {Q}_{d}=-Coxt*\left(\frac{{V}_{gs}-{V}_{TH}}{2}-\frac{3{V}_{ds}}{4}+\frac{{V}_{ds}{}^{2}}{8\left({V}_{gs}-{V}_{TH}-0.5{V}_{ds}\right)}\right)\\ {Q}_{s}={Q}_{c}-{Q}_{d}\end{array}$

where:

• Qg is the gate charge.

• Qb is the bulk charge.

• Qd is the drain charge.

• Qs is the source charge.

• ${Q}_{c}=-\left({Q}_{g}+{Q}_{b}\right)={Q}_{d}+{Q}_{s}$ is the charge in channel. Qc needs to be partitioned between Qd and Qs.

This table shows the relationship between the operational regions of the transistor and the gate, bulk, channel, drain, and source charges for a level-3 MOS.

Operational regionLevel-3 Charges Equations
Accumulation region, ${V}_{gb}<{V}_{FB}$$\begin{array}{l}{Q}_{g}=Coxt*\left({V}_{gb}-{V}_{FB}\right)-S{F}_{1}+S{F}_{2}\\ {Q}_{b}=-Coxt*\left({V}_{gb}-{V}_{FB}\right)-S{F}_{1}+S{F}_{2}\\ {Q}_{c}=0\\ {Q}_{d}=0\\ {Q}_{s}={Q}_{c}-{Q}_{d}\end{array}$
Depletion region, ${V}_{gs}<{V}_{TH}$$\begin{array}{l}{Q}_{g}=-0.5*Coxt*GAMM{A}^{2}*\left(1-\sqrt{1+\frac{4}{GAMM{A}^{2}}*\left({V}_{gb}-{V}_{FB}\right)}\right)-S{F}_{1}+S{F}_{2}\\ {Q}_{b}=0.5*Coxt*GAMM{A}^{2}*\left(1-\sqrt{1+\frac{4}{GAMM{A}^{2}}*\left({V}_{gb}-{V}_{FB}\right)}\right)+S{F}_{1}-S{F}_{2}\\ {Q}_{c}=0\\ {Q}_{d}=0\\ {Q}_{s}={Q}_{c}-{Q}_{d}\end{array}$
Saturation region, ${V}_{gs}-{V}_{TH}<{V}_{ds}$$\begin{array}{l}{Q}_{g}=Coxt*\left({V}_{gs}-{V}_{FB}-PHI+ETA*{V}_{dsat}-\frac{{V}_{dsat}}{2}+\frac{1+{F}_{B}}{12*{F}_{i}}*{V}_{dsat}^{2}\right)\\ {Q}_{b}=-Coxt*\left({V}_{TH}-{V}_{FB}-PHI+ETA*{V}_{dsat}-\frac{{F}_{b}}{2}*{V}_{ds}-\frac{{F}_{B}*\left(1+{F}_{B}\right)}{12*{F}_{i}}*{V}_{dsat}^{2}\right)\\ {Q}_{c}=-Coxt*\left({V}_{gs}-{V}_{TH}-\frac{1+{F}_{B}}{2}*{V}_{dsat}+\frac{{\left(1+{F}_{B}\right)}^{2}}{12*{F}_{i}}*{V}_{dsat}^{2}\right)\\ {Q}_{d}=0\\ {Q}_{s}={Q}_{c}-{Q}_{d}\end{array}$
Linear region, ${V}_{gs}-{V}_{TH}>{V}_{ds}$$\begin{array}{l}{Q}_{g}=Coxt*\left({V}_{gs}-{V}_{FB}-PHI+ETA*{V}_{ds}-\frac{{V}_{ds}}{2}+\frac{1+{F}_{B}}{12*{F}_{i}}*{V}_{ds}^{2}\right)\\ {Q}_{b}=-Coxt*\left({V}_{TH}-{V}_{FB}-PHI+ETA*{V}_{ds}+\frac{{F}_{B}}{2}*{V}_{ds}-\frac{{F}_{B}*\left(1+{F}_{B}\right)}{12*{F}_{i}}*{V}_{ds}^{2}\right)\\ {Q}_{c}=-Coxt*\left({V}_{gs}-{V}_{TH}-\frac{1+{F}_{B}}{2}*{V}_{ds}+\frac{{\left(1+{F}_{B}\right)}^{2}}{12*{F}_{i}}*{V}_{ds}^{2}\right)\\ {Q}_{d}=-Coxt*\left(\frac{{V}_{gs}-{V}_{TH}}{2}-\frac{3\left(1+{F}_{B}\right)}{2}*{V}_{ds}+\frac{{\left(1+{F}_{B}\right)}^{2}}{8*{F}_{i}}*{V}_{ds}^{2}\right)\\ {Q}_{s}={Q}_{c}-{Q}_{d}\end{array}$

where:

• Vdsat is the saturation voltage

• FB is the body effect coefficient

• ETA is the drain-source voltage threshold coefficient

• ${F}_{i}={V}_{gs}-{V}_{TH}-\frac{1+{F}_{B}}{2}*{V}_{ds}$

• $S{F}_{1}=-0.5*Coxt*GAMM{A}^{2}*\left(1-{\left(1+\frac{4}{GAMM{A}^{2}}*2\left({V}_{TH}-{V}_{bs}-{V}_{FB}\right)\right)}^{0.5}\right)$ and $S{F}_{2}=Coxt*\left({V}_{TH}-{V}_{FB}-PHI\right)$ are smoothing factors between depletion and accumulation regions to help with convergence.

### Temperature Dependence

The transconductance as a function of the transistor temperature is

$KP\left(T\right)=\frac{K{P}_{d}}{{\left(T}{{T}_{meas}}\right)}^{3/2}}$

Where:

• KPd is the geometry-adjusted transconductance.

• T is the transistor temperature. For more information, see Transistor Temperature.

• Tmeas is the parameter extraction temperature.

The surface potential as a function of the transistor temperature is

$\begin{array}{l}PHI\left(T\right)=\frac{T}{{T}_{meas}}\left(PHI+\frac{k{T}_{meas}}{q}\left(\mathrm{log}{\left(\frac{{T}_{meas}}{300.15}\right)}^{3}+\frac{q}{k}\left(\frac{1.115}{300.15}-\frac{E{G}_{{T}_{meas}}}{{T}_{meas}}\right)\right)\right)\\ \text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}-\frac{kT}{q}\left(\mathrm{log}{\left(\frac{T}{300.15}\right)}^{3}+\frac{q}{k}\left(\frac{1.115}{300.15}-\frac{E{G}_{T}}{T}\right)\right)\end{array}$

Where:

• PHI is the surface potential.

• k is the Boltzmann constant.

• q is the elementary charge on an electron, 1.6021918e-19 C.

• EG is the activation energy, such that:

• $E{G}_{{T}_{meas}}=1.16eV-\left(7.02e-4*{T}_{meas}{}^{2}\right)/\left({T}_{meas}+1108\right)$

• $E{G}_{T}=1.16eV-\left(7.02e-4*{T}^{2}\right)/\left(T+1108\right)$

The built-in voltage as a function of the transistor temperature is

$\begin{array}{l}VBI\left(T\right)=VTO+MTYPE*\left(\frac{PHI\left(T\right)-PHI}{2}-GAMMA\sqrt{PHI}\right)\\ \text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}+\frac{E{G}_{{T}_{meas}}-E{G}_{T}}{2}\end{array}$

Where:

• VBI is the built-in voltage.

• VTO is the threshold voltage. VTO depends on the value that you specify for the Threshold voltage, VTO parameter in the DC currents settings. If you specify a numerical value, VTO is evaluated as that value. If you specify a nonnumerical value (NAN) and you specify numerical values for both the Oxide thickness, TOX and Substrate doping, NSUB parameters in the Process settings, then VTO is evaluated as $\Phi -3.25+E{G}_{{T}_{meas}}/2+MTYPE*PHI/2-NSS*q*TOX/\left(3.9*{\epsilon }_{0}\right)+MTYPE*\left(GAMMA*\sqrt{PHI}+PHI\right)$, Where:

• Φ depends on the gate type, which you specify using the Gate type, TPG parameter. If you specify Aluminum (0), $\Phi =3.2$. Otherwise, $\Phi =3.25+E{G}_{{T}_{meas}}/2-MTYPE*TPG*E{G}_{{T}_{meas}}/2$, Where:

• MTYPE is the transistor type. For an P-channel MOSFET, MTYPE = -1.

• TPG represents the gate type and also depends on the option that you specify for the Gate type, TPG parameter in the Process settings. If you specify

• Opposite of substrate (1)TPG = 1

• Same as substrate (-1)TPG = -1

• NSS is the surface state density.

• TOX is the oxide thickness.

• ε0 is the permittivity of free space.

• GAMMA is the bulk threshold. GAMMA depends on the value that you specify for the Bulk threshold, GAMMA parameter in the DC currents settings. If you specify a numerical value, GAMMA is evaluated as that value. If you specify a nonnumerical value (NAN) and you specify numerical values for both the Oxide thickness, TOX and Substrate doping, NSUB parameters in the Process settings, then VTO is evaluated as $TOX*\sqrt{2*11.7*{\epsilon }_{0}*q*NSUB}/\left(3.9*{\epsilon }_{0}\right)$, where NSUB is the substrate doping.

The bulk saturation current as a function of the transistor temperature is

$IS\left(T\right)=I{S}_{d}*{e}^{\frac{-qE{G}_{T}}{ND*kT}\text{\hspace{0.17em}}+\text{\hspace{0.17em}}\frac{qE{G}_{{T}_{meas}}}{ND*k{T}_{meas}}}$

Where:

• ISd is the geometry-adjusted bulk saturation current.

• ND is the emission coefficient.

The bulk junction saturation current density as a function of the transistor temperature is

$JS\left(T\right)=J{S}_{d}*{e}^{\frac{-qE{G}_{T}}{ND*kT}\text{\hspace{0.17em}}+\text{\hspace{0.17em}}\frac{qE{G}_{{T}_{meas}}}{ND*k{T}_{meas}}}$

Where:

• JSd is the geometry-adjusted bulk junction saturation current density.

The bulk junction potential as a function of the transistor temperature is

$\begin{array}{l}PB\left(T\right)=\frac{PB+\frac{k{T}_{meas}}{q}\left(\mathrm{log}{\left(\frac{{T}_{meas}}{300.15}\right)}^{3}+\frac{q}{k}\left(\frac{1.115}{300.15}-\frac{E{G}_{{T}_{meas}}}{T}\right)\right)}{{T}_{meas}}{T}}\\ \text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}-\frac{kT}{q}\left(\mathrm{log}{\left(\frac{T}{300.15}\right)}^{3}+\frac{q}{k}\left(\frac{1.115}{300.15}-\frac{E{G}_{T}}{T}\right)\right)\end{array}$

Where:

• PB is the bulk junction potential.

The bulk-drain junction capacitance as a function of the transistor temperature is

$CBD\left(T\right)=CB{D}_{d}\frac{pbo+MJ*\left(4*{10}^{4}*\left(T-300.15\right)*pbo-\left(PB\left(T\right)-pbo\right)\right)}{pbo+MJ*\left(4*{10}^{4}*\left({T}_{meas}-300.15\right)*pbo-\left(PB-pbo\right)\right)}$

Where:

• CBDd is the geometry adjusted zero-bias bulk-drain capacitance.

• MJ is the bottom grading coefficient.

• $pbo=\frac{PB+\frac{k{T}_{meas}}{q}\left(\mathrm{log}{\left(\frac{{T}_{meas}}{300.15}\right)}^{3}+\frac{q}{k}\left(\frac{1.115}{300.15}-\frac{E{G}_{{T}_{meas}}}{T}\right)\right)}{{T}_{meas}}{300.15}}$

The block uses the CBD(T) equation to calculate:

• The bulk-source junction capacitance by substituting CBSd, the geometry-adjusted zero-bias bulk-source capacitance, for CBDd.

• The bottom junction capacitance by substituting CJd, the geometry-adjusted bottom capacitance per junction area for CBDd.

The relationship between the sidewall junction capacitance CJSW and the transistor temperature, T, is

$CJSW\left(T\right)=CJS{W}_{d}\frac{pbo+MJSW*\left(4*{10}^{4}*\left(T-300.15\right)*pbo-\left(PB\left(T\right)-pbo\right)\right)}{pbo+MJSW*\left(4*{10}^{4}*\left({T}_{meas}-300.15\right)*pbo-\left(PB-pbo\right)\right)}$

Where:

• CJSWd is the side geometry-adjusted sidewall capacitance per junction perimeter.

• MJSW is the side grading coefficient.

## Assumptions and Limitations

• The block does not support noise analysis.

• The block applies initial conditions across junction capacitors and not across the block ports.

## Ports

### Conserving

expand all

Electrical conserving port associated with the transistor gate terminal.

Electrical conserving port associated with the transistor drain terminal.

Electrical conserving port associated with the transistor source terminal.

Electrical conserving port associated with the transistor bulk terminal.

## Parameters

expand all

### Model Selection

MOSFET drain current model options:

#### Dependencies

The setting that you select for the MOS model affects the visibility of certain parameters in the DC Currents and Process settings.

### Dimensions

Transistor area factor for scaling. The value must be greater than 0.

Number of parallel MOS instances that the block represents. This parameter multiplies the output current and device charge. The value must be greater than 0.

Length of the channel between the source and drain.

Width of the channel between the source and drain.

Area of the transistor drain diffusion. The value must be greater than or equal to 0.

Area of the transistor source diffusion. The value must be greater than or equal to 0.

Perimeter of the transistor drain diffusion. The value must be greater than or equal to 0.

Perimeter of the transistor source diffusion. The value must be greater than or equal to 0.

### Resistors

Number of squares of resistance that make up the transistor drain diffusion. The value must be greater than or equal to 0. The block only uses this parameter value if you do not specify one or both of the Drain resistance, RD and Source resistance, RS parameter values, as described in Parameters Calculations.

Number of squares of resistance that make up the transistor source diffusion. The value must be greater than or equal to 0. The block only uses this parameter value if you do not specify one or both of the Drain resistance, RD and Source resistance, RS parameter values, as described in Parameters Calculations.

Transistor drain resistance. The value must be greater than or equal to 0.

Transistor source resistance. The value must be greater than or equal to 0.

Resistance per square of the transistor source and drain. Check Parameters Calculations to see when the block uses this parameter. The value must be greater than or equal to 0.

### DC Currents

Source-gate voltage above which the transistor produces a nonzero drain current. If you assign this parameter a value of NaN, the block calculates the value from the specified values of the Oxide thickness, TOX and Substrate doping, NSUB parameters. For more information about this calculation, see Temperature Dependence .

Derivative of drain current with respect to gate voltage. The value must be greater than or equal to 0. If you assign this parameter a value of NaN, the block calculates the value from the specified values of the Oxide thickness, TOX and Substrate doping, NSUB parameters. For more information about this calculation, see Level 1 Drain Current Model or Level 3 Drain Current Model as appropriate for the selected value of the MOS model parameter.

Body effect parameter, which relates the threshold voltage, VTH, to the body bias, VBS, as described in Level 1 Drain Current Model and Level 3 Drain Current Model. The value must be greater than or equal to 0. If you assign this parameter a value of NaN, the block calculates the value from the specified values of the Oxide thickness, TOX and Substrate doping, NSUB parameters. For more information about this calculation, see Level 1 Drain Current Model or Level 3 Drain Current Model as appropriate for the selected value of the MOS model parameter.

Twice the voltage at which the surface electron concentration becomes equal to the intrinsic concentration and the device transitions between depletion and inversion conditions. The value must be greater than or equal to 0. If you assign this parameter a value of NaN, the block calculates the value from the specified values of the Oxide thickness, TOX and Substrate doping, NSUB parameters. For more information about this calculation, see Level 1 Drain Current Model or Level 3 Drain Current Model as appropriate for the selected value of the MOS model parameter.

Channel-length modulation.

#### Dependencies

This parameter is only visible when you select Level 1 MOS for the MOS model parameter in the Model Selection settings.

Magnitude of the current that the junction approaches asymptotically for very large reverse bias levels. The value must be greater than or equal to 0.

Transistor emission coefficient or ideality factor. The value must be greater than 0.

Magnitude of the current per unit area that the junction approaches asymptotically for very large reverse bias levels. The value must be greater than or equal to 0.

Factor that controls the effect of transistor width on threshold voltage.

#### Dependencies

This parameter is only visible when you select Level 3 MOS for the MOS model parameter in the Model Selection settings.

Maximum drift velocity of the carriers.

#### Dependencies

This parameter is only visible when you select Level 3 MOS for the MOS model parameter in the Model Selection settings.

Fast surface state density adjusts the drain current for the mobility reduction caused by the gate voltage.

#### Dependencies

This parameter is only visible when you select Level 3 MOS for the MOS model parameter in the Model Selection settings.

Coefficient that controls how the drain voltage affects the mobility in the drain current calculation.

#### Dependencies

This parameter is only visible when you select Level 3 MOS for the MOS model parameter in the Model Selection settings.

Coefficient that controls how the gate voltage affects the mobility in the drain current calculation.

#### Dependencies

This parameter is only visible when you select Level 3 MOS for the MOS model parameter in the Model Selection settings.

Coefficient of channel-length modulation for the level 3 MOS model.

#### Dependencies

This parameter is only visible when you select Level 3 MOS for the MOS model parameter in the Model Selection settings.

### C-V

Options for modeling the gate capacitance:

• No intrinsic capacitance — Do not include gate capacitance in the model.

• Meyer gate capacitances — Model capacitances using Meyer gate capacitances.

• Charge conservation capacitances — Model capacitances using charge conservation capacitances.

Options for modeling the gate overlap capacitance:

• No — Do not include gate overlap capacitance in the model.

• Yes — Specify the gate-source, gate-drain, and gate-bulk capacitances.

#### Dependencies

Selecting Yes exposes related parameters.

Gate-source capacitance due to lateral diffusion of the source. The value must be equal to 0 or greater than or equal to Cmin. Cmin is a built-in model constant whose value is 1e-18.

#### Dependencies

This parameter is only visible when you select Yes for the Model gate overlap capacitance (CGSO, CGDO, CGBO) parameter.

Gate-drain capacitance due to lateral diffusion of the drain. The value must be equal to 0 or greater than or equal to Cmin. Cmin is a built-in model constant whose value is 1e-18.

#### Dependencies

This parameter is only visible when you select Yes for the Model gate overlap capacitance (CGSO, CGDO, CGBO) parameter.

Gate-bulk capacitance due to gate extending beyond the channel width. The value must be equal to 0 or greater than or equal to Cmin. Cmin is a built-in model constant whose value is 1e-18.

#### Dependencies

This parameter is only visible when you select Yes for the Model gate overlap capacitance (CGSO, CGDO, CGBO) parameter.

Options for modeling the junction capacitance:

• No — Do not include junction capacitance in the model.

• Yes — Specify zero-bias junction capacitance, junction potential, grading coefficient, forward-bias depletion and capacitance coefficient.

#### Dependencies

Selecting Yes exposes related parameters.

Capacitance between the bulk and the drain. The value must be equal to 0 or greater than or equal to Cmin. Cmin is a built-in model constant whose value is 1e-18.

#### Dependencies

This parameter is only visible when you select Yes for the Model junction capacitance (CBD, CBS) parameter.

Capacitance between the bulk and the source. The value must be equal to 0 or greater than or equal to Cmin. Cmin is a built-in model constant whose value is 1e-18.

#### Dependencies

This parameter is only visible when you select Yes for the Model junction capacitance (CBD, CBS) parameter.

Potential across the bulk junction. This parameter is only visible when you select Yes for the Model junction capacitance (CBD, CBS) parameter. The value must be equal to 0 or greater than or equal to VJmin. VJmin is a built-in model constant whose value is 0.01.

#### Dependencies

This parameter is only visible when you select Yes for the Model junction capacitance (CBD, CBS) parameter.

Zero-bias bulk junction bottom capacitance per junction area. The value must be equal to 0 or greater than or equal to Cmin. Cmin is a built-in model constant whose value is 1e-18.

#### Dependencies

This parameter is only visible when you select Yes for the Model junction capacitance (CBD, CBS) parameter.

Transistor bottom grading coefficient. The value must be equal to 0 or less than MGmax. MGmax is a built-in model constant whose value is 0.9.

#### Dependencies

This parameter is only visible when you select Yes for the Model junction capacitance (CBD, CBS) parameter.

Zero-bias bulk junction sidewall capacitance per junction perimeter. The value must be equal to 0 or greater than or equal to Cmin. Cmin is a built-in model constant whose value is 1e-18.

#### Dependencies

This parameter is only visible when you select Yes for the Model junction capacitance (CBD, CBS) parameter.

Transistor sidewall grading coefficient. The value must be equal to 0 or less than MGmax. MGmax is a built-in model constant whose value is 0.9.

#### Dependencies

This parameter is only visible when you select Yes for the Model junction capacitance (CBD, CBS) parameter.

Fitting coefficient that quantifies the decrease of the depletion capacitance with applied voltage. The value must be equal to 0 or less than or equal to FCmax. FCmax is a built-in model constant whose value is 0.95.

#### Dependencies

This parameter is only visible when you select Yes for the Model junction capacitance (CBD, CBS) parameter.

Options for specifying initial conditions:

• No — Do not specify an initial condition for the model.

• Yes — Specify the initial transistor voltage.

Note

The block applies the initial transistor voltage across the junction capacitors and not across the ports.

#### Dependencies

To enable this parameter, set either:

• Model gate capacitance (CGS, CGD, CGB) to No intrinsic capacitance and either or both Model gate overlap capacitance (CGSO, CGDO, CGBO) and Model junction capacitance (CBD, CBS) to Yes.

• Model gate capacitance (CGS, CGD, CGB) to Meyer gate capacitances or Charge conservation capacitances.

Drain-source voltage at the start of the simulation.

#### Dependencies

This parameter is only visible when you select Yes for the Specify initial condition parameter.

Gate-source voltage at the start of the simulation.

#### Dependencies

This parameter is only visible when you select Yes for the Specify initial condition parameter.

Bulk-source voltage at the start of the simulation.

#### Dependencies

This parameter is only visible when you select Yes for the Specify initial condition parameter.

### Process

Thickness of the gate oxide. The value must be greater than or equal to 0.

Length of lateral diffusion.

Zero-bias surface mobility coefficient.

Substrate doping. The value must be greater than or equal to 1.45e10 (the carrier concentration of intrinsic silicon).

MOSFET gate materials (as compared to the substrate):

• Opposite of substrate — The gate material is the opposite of the substrate. This means that TPG = 1 in the device equations. This is the default option.

• Same as substrate — The gate material is the same as the substrate. This means that TPG = –1 in the device equations.

• Aluminum — The gate material is aluminum. This means that TPG = 0 in the device equations.

Surface state density.

Junction depth.

#### Dependencies

This parameter is only visible when you select Level 3 MOS for the MOS model parameter in the Model Selection settings.

### Temperature

Select one of these options for modeling the transistor temperature dependence:

• Device temperature — Use the device temperature to model temperature dependence.

• Fixed temperature — Use a temperature that is independent of the circuit temperature to model temperature dependence.

#### Dependencies

Selecting Device temperature exposes the Offset local circuit temperature, TOFFSET parameter. Selecting Fixed temperature exposes the Fixed circuit temperature, TFIXED parameter.

Transistor simulation temperature. The value must be greater than 0 K.

#### Dependencies

This parameter is only visible when you select Fixed temperature for the Model temperature dependence using parameter.

The temperature at which the transistor parameters are measured. The value must be greater than 0 K.

Amount by which the transistor temperature differs from the circuit temperature.

#### Dependencies

This parameter is only visible when you select Device temperature for the Model temperature dependence using parameter.

## References

[1] G. Massobrio and P. Antognetti. Semiconductor Device Modeling with SPICE. 2nd Edition. New York: McGraw-Hill, 1993.

[2] Ping Yang, et al. ‘An Investigation of the Charge Conservation Problem for MOSFET Circuit Simulation’. IEEE Journal of Solid-State Circuits, vol. 18, no. 1, Feb. 1983, pp. 128–38. DOI.org (Crossref), doi:10.1109/JSSC.1983.1051909.

## Extended Capabilities

### Functions

Introduced in R2009a