MATLAB AXI Master
Access on-board memory locations from MATLAB or Simulink by using the MATLAB AXI master IP in your FPGA design. This IP connects to slave memory locations on the board. The IP also responds to read and write commands from MATLAB or Simulink, over JTAG, PCI Express, or Ethernet cable.
To use this feature, you must download a hardware support package for your FPGA board. More documentation for this feature is included with the support package installation. See support package documentation:
For information on downloading support packages, see Download FPGA Board Support Package.
High-level steps for accessing memory on an FPGA board from MATLAB or Simulink.