Create a Folder for Your Tutorial Files
Set up a writable working folder outside your MATLAB® installation
folder to store files that will be generated as you complete your
tutorial work. The tutorial instructions assume that you create the
hdlfilter_tutorials on drive C.
Design an IIR Filter in Filter Designer
This tutorial guides you through the steps for designing an IIR filter, generating Verilog code for the filter, and verifying the Verilog code with a generated test bench.
This section guides you through the procedure of designing and creating a filter for an IIR filter. This section assumes that you are familiar with the MATLAB user interface and the Filter Designer.
Start the MATLAB software.
Set your current folder to the folder you created in Create a Folder for Your Tutorial Files.
Start the Filter Designer by entering the
filterDesignercommand in the MATLAB Command Window. The Filter Design & Analysis Tool dialog box appears.
In the Filter Design & Analysis Tool dialog box, set the following filter options:
Option Value Response Type
Click Design Filter. The Filter Designer creates a filter for the specified design. The following message appears in the Filter Designer status bar when the task is complete.
Designing Filter... Done
For more information on designing filters with the Filter Designer, see Use Filter Designer with DSP System Toolbox Software.
Quantize the IIR Filter
You should quantize filters for HDL code generation. To quantize your filter,
Open the IIR filter design you created in Design an IIR Filter in Filter Designer if it is not already open.
Click the Set Quantization Parameters button in the left-side toolbar. The Filter Designer displays the Filter arithmetic list in the bottom half of its dialog box.
Fixed-pointfrom the list. The Filter Designer displays the first of three tabbed panels of its dialog box.
Use the quantization options to test the effects of various settings on the performance and accuracy of the quantized filter.
Select the Filter Internals tab and set Rounding mode to
Floorand Overflow Mode to
Click Apply. The quantized filter appears as follows.
For more information on quantizing filters with the Filter Designer, see Use Filter Designer with DSP System Toolbox Software.
Configure and Generate VHDL Code
After you quantize your filter, you are ready to configure coder options and generate VHDL code. This section guides you through starting the Filter Design HDL Coder™ UI, setting options, and generating the VHDL code and a test bench for the IIR filter you designed and quantized in Design an IIR Filter in Filter Designer and Quantize the IIR Filter.
Start the Filter Design HDL Coder UI by selecting Targets > Generate HDL in the Filter Designer dialog box. The Filter Designer displays the Generate HDL dialog box.
In the Name text box of the Target pane, type
iir. This option names the VHDL entity and the file that contains the VHDL code for the filter.
Select the Global settings tab of the UI. Then select the General tab of the Additional settings section.
In the Comment in header text box, type
Tutorial - IIR Filter. The coder adds the comment to the end of the header comment block in each generated file.
Select the Ports tab. The Ports pane appears.
Clear the check box for the Add output register option. The Ports pane now appears as in the following figure.
Select the Advanced tab. The Advanced pane appears.
Select the Use 'rising_edge' for registers option. The Advanced pane now appears as in the following figure.
Click the Test bench tab in the Generate HDL dialog box. In the File name text box, replace the default name with
iir_tb. This option names the generated test bench file.
In the Generate HDL dialog box, click Generate to start the code generation process. When code generation completes, click OK to close the dialog box.
The coder displays the following messages in the MATLAB Command Window as it generates the filter and test bench VHDL files:
### Starting VHDL code generation process for filter: iir ### Starting VHDL code generation process for filter: iir ### Generating: H:\hdlsrc\iir.vhd ### Starting generation of iir VHDL entity ### Starting generation of iir VHDL architecture ### Second-order section, # 1 ### Second-order section, # 2 ### First-order section, # 3 ### HDL latency is 1 samples ### Successful completion of VHDL code generation process for filter: iir ### Starting generation of VHDL Test Bench ### Generating input stimulus ### Done generating input stimulus; length 2172 samples. ### Generating Test bench: H:\hdlsrc\filter_tb.vhd ### Please wait ... ### Done generating VHDL Test Bench ### Starting VHDL code generation process for filter: iir ### Starting VHDL code generation process for filter: iir ### Generating: H:\hdlsrc\iir.vhd ### Starting generation of iir VHDL entity ### Starting generation of iir VHDL architecture ### Second-order section, # 1 ### Second-order section, # 2 ### First-order section, # 3 ### HDL latency is 1 samples ### Successful completion of VHDL code generation process for filter: iir
As the messages indicate, the coder creates the folder
hdlsrcunder your current working folder and places the files
iir_tb.vhdin that folder.
Observe that the messages include hyperlinks to the generated code and test bench files. By clicking these hyperlinks, you can open the code files directly into the MATLAB Editor.
The generated VHDL code has the following characteristics:
VHDL entity named
Registers that use asynchronous resets when the reset signal is active high (1).
Ports have the following default names:
VHDL Port Name Input
Clock enable input
An extra register for handling filter input.
Clock input, clock enable input, and reset ports are of type
STD_LOGICand data input and output ports are of type
Coefficients are named
nis the coefficient number, starting with 1.
Type-safe representation is used when zeros are concatenated:
'0' & '0'...
Registers are generated with the
rising_edgefunction rather than the statement
ELSIF clk'event AND clk='1' THEN.
'_process'is appended to process names.
The generated test bench:
Is a portable VHDL file.
Forces clock, clock enable, and reset input signals.
Forces the clock enable input signal to active high.
Drives the clock input signal high (1) for 5 nanoseconds and low (0) for 5 nanoseconds.
Forces the reset signal for two cycles plus a hold time of 2 nanoseconds.
Applies a hold time of 2 nanoseconds to data input signals.
For an IIR filter, applies impulse, step, ramp, chirp, and white noise stimulus types.
Explore the Generated VHDL Code
Get familiar with the generated VHDL code by opening and browsing
through the file
iir.vhd in an ASCII or HDL simulator
Open the generated VHDL filter file
iir. This line identifies the VHDL module, using the value you specified for the Name option in the Target pane. See step 2 in Configure and Generate VHDL Code.
Tutorial. This section is where the coder places the text you entered for the Comment in header option. See step 5 in Configure and Generate VHDL Code.
HDL Code. This section lists coder options you modified in Configure and Generate VHDL Code.
Filter Settings. This section of the VHDL code describes the filter design and quantization settings as you specified in Design an IIR Filter in Filter Designer and Quantize the IIR Filter.
ENTITY. This line names the VHDL entity, using the value you specified for the Name option in the Target pane. See step 2 in Configure and Generate VHDL Code.
PORTdeclaration defines the filter's clock, clock enable, reset, and data input and output ports. The ports for clock, clock enable, reset, and data input and output signals are named with default character vectors.
CONSTANT. This code defines the coefficients. They are named using the default naming scheme,
mis the coefficient number, and
nis the section number.
SIGNAL. This code defines the signals of the filter.
input_reg_processincludes the default
'_process'. This code reads the filter input from an input register. Code for this register is generated by default. In step 7 in Configure and Generate VHDL Code, you cleared the Add output register option, but left the Add input register option selected.
IF reset. This code asserts the reset signal. The default, active high (1), was specified. Also note that the
PROCESSblock applies the default asynchronous reset style when generating VHDL code for registers.
ELSIF. This code checks for rising edges when the filter operates on registers. The
rising_edgefunction is used as you specified in the Advanced pane of the Generate HDL dialog box. See step 10 in Configure and Generate VHDL Code.
Section 1. This section is where second-order section 1 data is filtered. Similar sections of VHDL code apply to another second-order section and a first-order section.
filter_out. This code drive the filter output data.
Verify the Generated VHDL Code
This section explains how to verify the generated VHDL code for the IIR filter with the generated VHDL test bench. This tutorial uses the Mentor Graphics® ModelSim® simulator as the tool for compiling and simulating the VHDL code. You can use other HDL simulation tool packages.
To verify the filter code, complete the following steps:
Start your simulator. When you start the Mentor Graphics ModelSim simulator, a screen display similar to the following appears.
Set the current folder to the folder that contains your generated VHDL files. For example:
If desired, create a design library to store the compiled VHDL entities, packages, architectures, and configurations. In the Mentor Graphics ModelSim simulator, you can create a design library with the
Compile the generated filter and test bench VHDL files. In the Mentor Graphics ModelSim simulator, you compile VHDL code with the
vcomcommand. The following the commands compile the filter and filter test bench VHDL code.
vcom iir.vhd vcom iir_tb.vhd
The following screen display shows this command sequence and informational messages displayed during compilation.
Load the test bench for simulation. The procedure for loading the test bench varies depending on the simulator you are using. In the Mentor Graphics ModelSim simulator, you load the test bench for simulation with the
vsimcommand. For example:
The following display shows the results of loading
Open a display window for monitoring the simulation as the test bench runs. In the Mentor Graphics ModelSim simulator, use the following command to open a wave window and view the results of the simulation as HDL waveforms.
add wave *
The following wave window displays.
To start running the simulation, issue the start simulation command for your simulator. For example, in the Mentor Graphics ModelSim simulator, you can start a simulation with the
The following display shows the
run -allcommand being used to start a simulation.
As your test bench simulation runs, watch for error messages. If error messages appear, interpret them as they pertain to your filter design and the HDL code generation options you selected. Determine whether the results are expected based on the customizations you specified when generating the filter VHDL code.
The warning messages that note
Time: 0 nsin the preceding display are not errors and you can ignore them.
The failure message that appears in the preceding display is not flagging an error. If the message includes the text
Test Complete, the test bench has run to completion without encountering an error. The
Failurepart of the message is tied to the mechanism that the coder uses to end the simulation.
The following wave window shows the simulation results as HDL waveforms.