Language-Specific Identifiers and Postfix Parameters

This section contains parameters in the Clock Settings section of theHDL Code Generation > Global Settings pane of the Configuration Parameters dialog box. Using these parameters, you can specify the entity, module, and package name postfix, and the prefix for module names.

Entity conflict postfix

Specify the text as a character vector to resolve duplicate VHDL^® entity, Verilog^® or SystemVerilog module names in generated code.

Settings

Default: _block

The specified postfix resolves duplicate VHDL entity, Verilog or SystemVerilog module names.

For example, if HDL Coder™ detects two entities with the name MyFilter, the coder names the first entity MyFilter and the second entity MyFilter_block.

Command-Line Information

Property: EntityConflictPostfix

Type: character vector

Value: A valid character vector in the target language

Default: '_block'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can specify this property when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir', ... 
        'EntityConflictPostfix','_entity')

When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','EntityConflictPostfix','_entity')
makehdl('sfir_fixed/symmetric_fir')
```

Package postfix

Specify a text as a character vector to append to the model or subsystem name to form name of a package file.

Settings

Default: _pkg

HDL Coder applies this option only if a package file is required for the design.

Dependency

This option is enabled when the target language (specified by the Language option) is VHDL or SystemVerilog.
This option is enabled when the target language (specified by the Language option) is Verilog, and the Multi-file test bench option is selected.
This option is ignored, when the HDL Coding Standard is set to Industry.

Command-Line Information

Property: PackagePostfix

Type: character vector

Value: A character vector that is legal in a VHDL package file name

Default: '_pkg'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can specify this property when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir', ... 
        'PackagePostfix','_pkg')

When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','PackagePostfix','_pkg')
makehdl('sfir_fixed/symmetric_fir')
```

Reserved word postfix

Specify a text as a character vector to append to value names, postfix values, or labels that are VHDL, Verilog or SystemVerilog reserved words.

Settings

Default: _rsvd

The reserved word postfix is applied to identifiers (for entities, signals, constants, or other model elements) that conflict with VHDL or Verilog reserved words. For example, if your generating model contains a signal named mod, HDL Coder adds the postfix _rsvd to form the name mod_rsvd.

Command-Line Information

Property: ReservedWordPostfix

Type: character vector

Default: '_rsvd'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can specify this property when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir', ... 
        'ReservedWordPostfix','_reserved')

When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','ReservedWordPostfix','_reserved)
makehdl('sfir_fixed/symmetric_fir')
```

Module name prefix

Specify a prefix for every module or entity name in the generated HDL code.

Settings

Default: ''

Specify a prefix for every module or entity name in the generated HDL code. HDL Coder also applies this prefix to generated script file names.

You can specify the module name prefix to avoid name collisions if you plan to instantiate the generated HDL code multiple times in a larger system.

Command-Line Information

Property: ModulePrefix

Type: character vector

Default: ''

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

Suppose you have a DUT, myDut, containing an internal module, myUnit. You can prefix the modules within your design with unit1_ by using either of these methods.

Pass the property as an argument to the makehdl function.

makehdl('myDUT', ... 
        'ModulePrefix','unit1_')

When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.
```
hdlset_param('myUnit/myDUT','ModulePrefix','unit1_')
makehdl('myDUT')
```

In the generated code, your HDL module names are unit1_myDut and unit1_myUnit, with corresponding HDL file names. Generated script file names also have the unit1_ prefix.

Pipeline postfix

Specify the postfix as a character vector to append to names of input or output pipeline registers generated for pipelined block implementations.

Settings

Default: '_pipe'

You can specify a generation of input and/or output pipeline registers for selected blocks. The Pipeline postfix option defines a character vector that HDL Coder appends to names of input or output pipeline registers when generating code.

Command-Line Information

Property: PipelinePostfix

Type: character vector

Default: '_pipe'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

Suppose you specify a pipelined output implementation for a Product block in a model, as in the following code:

 hdlset_param('sfir_fixed/symmetric_fir/Product','OutputPipeline', 2)

To append a postfix 'testpipe' to the generated pipeline register names, use either of these methods:

Pass the property as an argument to the makehdl function.
```
makehdl(gcb,'PipelinePostfix','testpipe')
```
When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.
```
hdlset_param(gcs,'PipelinePostfix','testpipe')
makehdl('myDUT')
```

The following excerpt from generated VHDL code shows process the PROCESS code, with postfixed identifiers, that implements two pipeline stages:

Product_outtestpipe_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      Product_outtestpipe_reg <= (OTHERS => to_signed(0, 33));
    ELSIF clk'EVENT AND clk = '1' THEN
      IF enb = '1' THEN
        Product_outtestpipe_reg(0) <= Product_out1;
        Product_outtestpipe_reg(1) <= Product_outtestpipe_reg(0);
      END IF;
    END IF;
  END PROCESS Product_outtestpipe_process;