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Debug IP Core Using FPGA Data Capture

This example shows how to debug an IP core you generate in HDL Coder™ using only FPGA Data Capture as well as both AXI Manager and FPGA Data Capture together.

Requirements

Introduction

Monitoring IP core internal signals while a design is running on real hardware is useful because you can debug and analyze the design. This example illustrates how to use the FPGA Data Capture to capture internal signals of the generated IP core in MATLAB®.

This example shows how to use FPGA Data Capture in blocking and nonblocking modes. For more information on capture modes, see CaptureMode (HDL Verifier Support Package for Xilinx FPGA Boards). Nonblocking mode allows simultaneous use of AXI Manager and FPGA Data Capture over a JTAG interface. Blocking mode suspends MATLAB execution, so you cannot use other applications when you use this mode. By contrast, nonblocking mode allows you to use AXI Manager to configure the IP core while FPGA Data Capture captures data from the hardware.

Open the model.

open_system('hdlcoder_led_blinking_data_capture');

This example implements the led_counter subsystem on the hardware. This subsystem models a counter that causes LEDs to blink on the hardware. Two input ports, Blink_frequency and Blink_direction, are control ports that determine the LED blink frequency and direction, respectively. The output port LED connects to the LEDs on the hardware. You can use the output port Read_back to read data back to MATLAB.

In the led_counter subsystem, several internal signals are test points. HDL Coder routes those internal signals out of the DUT and into the IP core wrapper so that the signals can be connected to the FPGA Data Capture HDL IP.

open_system('hdlcoder_led_blinking_data_capture/led_counter');

Generate HDL IP Core

Start HDL Workflow Advisor from the model and run through the IP Core Generation workflow. For a step-by-step guide, see Getting Started with Targeting Xilinx Zynq Platform.

1. In step 1.1, set Target workflow to IP Core Generation and Target platform to Xilinx Zynq ZC702 evaluation kit. Click Run This Task.

2. In step 1.2, set Reference design to Default system and Insert JTAG AXI Manager (HDL Verifier required) to on. Click Run This Task.

3. In step 1.3, select Enable HDL DUT output port generation for test points.

4. In step 1.3, set the interface of the blinkfrequency, blinkdirection, led_output, and count ports to FPGA Data Capture - JTAG. Click Run This Task.

5. Run through the remaining workflow steps to generate the HDL IP and program the target device.

Capture and Display Data from IP Core

Next, capture data from the Zynq board.

Locate the FPGA Data Capture launch script. For this example, the script is in your HDL code generation directory: hdl_prj/ip_core/led_count_ip_v1_0/fpga_data_capture/launchDataCaptureApp.m. You can also locate this script in the code generation report.

Run the launchDataCaptureApp script in MATLAB. Add the script directory to the MATLAB path or change the current working folder.

Capture Data in Blocking Mode

Execute the script to launch the FPGA Data Capture app. By default, FPGA Data Capture works in blocking mode. To capture data from the FPGA without setting a trigger condition, click Capture Data.

Alternatively, you can capture data with a trigger condition. For example, set the trigger condition led_counter == 0 and the trigger position 32. Then, click Capture Data again.

Capture Data in Nonblocking Mode

Execute the script to launch the FPGA Data Capture app and create the fpgadc_obj object in the workspace. Change the capture mode to nonblocking by executing the following command at the MATLAB command prompt.

fpgadc_obj.CaptureMode = 'nonblocking';

FPGA Data Capture in nonblocking mode allows simultaneous use of FPGA Data Capture and AXI Manager. For more information, see Simultaneous Use of FPGA Data Capture and AXI Manager (HDL Verifier Support Package for Xilinx FPGA Boards). Now set a trigger condition where led_blink_direction == 1 and set a trigger position of 512. Then, click Capture Data.

FPGA Data Capture waits for the trigger condition. As FPGA Data Capture allows AXI Manager to perform read and write operations in nonblocking mode.

Next, in FPGA Data Capture, set tp_blinkdirection to High. Then, create an AXI Manager object in MATLAB.

axi_manager_obj = aximanager('Xilinx');
axi_manager_obj.writememory('0x00000104',1);

FPGA Data Capture captures the data in the Logic Analyzer. The figure shows the change in the blink direction.