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Control the Scope of Delay Balancing

This example shows how to balance delays in specific parts of a design, without balancing delays on the entire design.

You can programmatically balance delays by using the BalanceDelays HDL block property to balance the additional delays introduced by HDL Coder™ for certain block implementations and optimizations. You can enable or disable this property on individual subsystems or certain blocks in your model. For example, in a design containing a data path and a control path, you can apply delay balancing only on the data path of the design, such as on the paths that require data synchronization. These examples shows how to use BalanceDelays at the block or subsystem level to control how and where HDL Coder balances delays:

  1. hdlcoder_localdelaybalancing.slx shows how to disable delay balancing on user-defined stable control paths.

  2. hdlcoder_localdelaybalancing_sharing.slx shows how to apply HDL optimizations like resource sharing in the presence of complicated control paths that require carefully constrained delay balancing.

Constrain Delay Balancing to the Data Path

The example model hdlcoder_localdelaybalancing.slx has two subsystems under the device under test (DUT) subsystem, hdlcoder_localdelaybalancing/Subsystem, param_control and symmetric_fir, which contain the control logic and the data path, respectively.

bdclose('all');
open_system('hdlcoder_localdelaybalancing');
open_system('hdlcoder_localdelaybalancing/Subsystem');

To the optimize timing results, each subsystem has one block that has one output pipeline register.

hdldispblkparams('hdlcoder_localdelaybalancing/Subsystem/param_control/And');
hdldispblkparams('hdlcoder_localdelaybalancing/Subsystem/symmetric_fir/Add');
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
HDL Block Parameters ('hdlcoder_localdelaybalancing/Subsystem/param_control/And')
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

Implementation

	Architecture : default

Implementation Parameters

	OutputPipeline : 1


%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
HDL Block Parameters ('hdlcoder_localdelaybalancing/Subsystem/symmetric_fir/Add')
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

Implementation

	Architecture : Linear

Implementation Parameters

	OutputPipeline : 1

Enable the generation of the validation model, generate HDL code using the makehdl function, and open the validation model to the param_control subsystem.

hdlset_param('hdlcoder_localdelaybalancing', 'GenerateValidationModel', 'on');
makehdl('hdlcoder_localdelaybalancing/Subsystem');
load_system('gm_hdlcoder_localdelaybalancing_vnl');
set_param('gm_hdlcoder_localdelaybalancing_vnl', 'SimulationCommand', 'update');
Simulink.BlockDiagram.expandSubsystem('gm_hdlcoder_localdelaybalancing_vnl/Subsystem/param_control/params');
open_system('gm_hdlcoder_localdelaybalancing_vnl/Subsystem/param_control');
### Generating HDL for 'hdlcoder_localdelaybalancing/Subsystem'.
### Using the config set for model <a href="matlab:configset.showParameterGroup('hdlcoder_localdelaybalancing', { 'HDL Code Generation' } )">hdlcoder_localdelaybalancing</a> for HDL code generation parameters.
### Running HDL checks on the model 'hdlcoder_localdelaybalancing'.
### Begin compilation of the model 'hdlcoder_localdelaybalancing'...
### Applying HDL optimizations on the model 'hdlcoder_localdelaybalancing'...
### The code generation and optimization options you have chosen have introduced additional pipeline delays.
### The delay balancing feature has automatically inserted matching delays for compensation.
### The DUT requires an initial pipeline setup latency. Each output port experiences these additional delays.
### Output port 1: 1 cycles.
### Output port 2: 1 cycles.
### Output port 3: 1 cycles.
### Working on... <a href="matlab:configset.internal.open('hdlcoder_localdelaybalancing', 'GenerateModel')">GenerateModel</a>
### Begin model generation.
### Model generation complete.
### Generating new validation model: <a href="matlab:open_system('hdlsrc/hdlcoder_localdelaybalancing/gm_hdlcoder_localdelaybalancing_vnl')">gm_hdlcoder_localdelaybalancing_vnl</a>.
### Validation model generation complete.
### Begin VHDL Code Generation for 'hdlcoder_localdelaybalancing'.
### Working on hdlcoder_localdelaybalancing/Subsystem/param_control/params as hdlsrc/hdlcoder_localdelaybalancing/params.vhd.
### Working on hdlcoder_localdelaybalancing/Subsystem/param_control as hdlsrc/hdlcoder_localdelaybalancing/param_control.vhd.
### Working on hdlcoder_localdelaybalancing/Subsystem/symmetric_fir as hdlsrc/hdlcoder_localdelaybalancing/symmetric_fir.vhd.
### Working on hdlcoder_localdelaybalancing/Subsystem as hdlsrc/hdlcoder_localdelaybalancing/Subsystem.vhd.
### Code Generation for 'hdlcoder_localdelaybalancing' completed.
### Creating HDL Code Generation Check Report file:///tmp/Bdoc22b_2054784_3453254/tp59df1693/hdlcoder-ex13756842/hdlsrc/hdlcoder_localdelaybalancing/Subsystem_report.html
### HDL check for 'hdlcoder_localdelaybalancing' complete with 0 errors, 0 warnings, and 0 messages.
### HDL code generation complete.

Delay balancing is enabled globally by default and inserts matching delays on both the control path and the data path, as shown in the validation model. For more information on the validation model, see Generated Model and Validation Model.

In this example, only the data path, symmetric_fir, requires data synchronization. The inputs u1 through u4 to the param_control subsystem are constant inputs that are coefficients to the FIR filter. The input paths through the DUT subsystem for these coefficients are stable and do not have to synchronize with each other or with the processed data. As a result, you can disable delay balancing for the input ports with constant inputs to the control logic to save on hardware resources. To achieve this, set the HDL block property BalanceDelays for Inport blocks u1 through u4 of the DUT subsystem to off. Because the stable paths propagate through to the lower-level hierarchy in the DUT subsystem, you do not need to disable this property for lower-level Inport blocks inside the param_control or symmetric_fir subsystems.

hdlset_param('hdlcoder_localdelaybalancing/Subsystem/u1', 'BalanceDelays', 'off');
hdlset_param('hdlcoder_localdelaybalancing/Subsystem/u2', 'BalanceDelays', 'off');
hdlset_param('hdlcoder_localdelaybalancing/Subsystem/u3', 'BalanceDelays', 'off');
hdlset_param('hdlcoder_localdelaybalancing/Subsystem/u4', 'BalanceDelays', 'off');

Close the validation model, generate HDL code using the makehdl function, and open the new validation model to the param_control subsystem.

bdclose('gm_hdlcoder_localdelaybalancing_vnl');
hdlset_param('hdlcoder_localdelaybalancing', 'ValidationModelNameSuffix', '_vnl_DBoff')
makehdl('hdlcoder_localdelaybalancing/Subsystem');
load_system('gm_hdlcoder_localdelaybalancing_vnl_DBoff');
set_param('gm_hdlcoder_localdelaybalancing_vnl_DBoff', 'SimulationCommand', 'update');
Simulink.BlockDiagram.expandSubsystem('gm_hdlcoder_localdelaybalancing_vnl_DBoff/Subsystem/param_control/params');
open_system('gm_hdlcoder_localdelaybalancing_vnl_DBoff/Subsystem/param_control');
### Generating HDL for 'hdlcoder_localdelaybalancing/Subsystem'.
### Using the config set for model <a href="matlab:configset.showParameterGroup('hdlcoder_localdelaybalancing', { 'HDL Code Generation' } )">hdlcoder_localdelaybalancing</a> for HDL code generation parameters.
### Running HDL checks on the model 'hdlcoder_localdelaybalancing'.
### Begin compilation of the model 'hdlcoder_localdelaybalancing'...
### Applying HDL optimizations on the model 'hdlcoder_localdelaybalancing'...
### The code generation and optimization options you have chosen have introduced additional pipeline delays.
### The delay balancing feature has automatically inserted matching delays for compensation.
### The DUT requires an initial pipeline setup latency. Each output port experiences these additional delays.
### Output port 1: 1 cycles.
### Output port 2: 1 cycles.
### Output port 3: 1 cycles.
### Working on... <a href="matlab:configset.internal.open('hdlcoder_localdelaybalancing', 'GenerateModel')">GenerateModel</a>
### Begin model generation.
### Model generation complete.
### Generating new validation model: <a href="matlab:open_system('hdlsrc/hdlcoder_localdelaybalancing/gm_hdlcoder_localdelaybalancing_vnl_DBoff')">gm_hdlcoder_localdelaybalancing_vnl_DBoff</a>.
### Validation model generation complete.
### Begin VHDL Code Generation for 'hdlcoder_localdelaybalancing'.
### Working on hdlcoder_localdelaybalancing/Subsystem/param_control/params as hdlsrc/hdlcoder_localdelaybalancing/params.vhd.
### Working on hdlcoder_localdelaybalancing/Subsystem/param_control as hdlsrc/hdlcoder_localdelaybalancing/param_control.vhd.
### Working on hdlcoder_localdelaybalancing/Subsystem/symmetric_fir as hdlsrc/hdlcoder_localdelaybalancing/symmetric_fir.vhd.
### Working on hdlcoder_localdelaybalancing/Subsystem as hdlsrc/hdlcoder_localdelaybalancing/Subsystem.vhd.
### Code Generation for 'hdlcoder_localdelaybalancing' completed.
### Creating HDL Code Generation Check Report file:///tmp/Bdoc22b_2054784_3453254/tp59df1693/hdlcoder-ex13756842/hdlsrc/hdlcoder_localdelaybalancing/Subsystem_report.html
### HDL check for 'hdlcoder_localdelaybalancing' complete with 0 errors, 0 warnings, and 0 messages.
### HDL code generation complete.

Now delay balancing is only active in the data path subsystem and the generated model and code do not contain any delays in the control path subsystem.

Localize Delay Balancing and Resource Sharing

The resource sharing optimization saves area usage in the final HDL implementation, at the cost of introducing a cycle of latency for each sharing group. This additional latency is usually balanced during delay balancing so that the numerics and functionality of the algorithm are preserved. One of the restrictions of resource sharing is that it cannot be applied on a subsystem within a feedback loop. Thus, if resource sharing is specified for a subsystem within a loop, then the optimization will fail. You can observe this in hdlcoder_localdelaybalancing_sharing.slx, where hdlcoder_localdelaybalancing_sharing/Subsystem/Subsystem is within a feedback loop.

bdclose('all');
load_system('hdlcoder_localdelaybalancing_sharing');
open_system('hdlcoder_localdelaybalancing_sharing/Subsystem');

However, in this design, you may know that the feedback loop is rarely used since the control signal causes the switch block, hdlcoder_localdelaybalancing_sharing/Subsystem/Subsystem/Switch, to choose the top input, the feed-forward path, most of the time. This user insight implies that it is fine to go ahead with resource sharing in this subsystem and disregard the feedback loop in the parent subsystem. In such cases, if you wish to ignore feedback loops during delay balancing, you must turn off delay balancing in the subsystem containing the feedback loop. This enables HDL Coder (TM) to ignore the feedback loop and proceed with resource sharing.

hdlset_param('hdlcoder_localdelaybalancing_sharing', 'BalanceDelays', 'off');
hdlset_param('hdlcoder_localdelaybalancing_sharing/Subsystem', 'BalanceDelays', 'off');
hdlset_param('hdlcoder_localdelaybalancing_sharing/Subsystem/Subsystem', 'BalanceDelays', 'on');
makehdl('hdlcoder_localdelaybalancing_sharing/Subsystem');
load_system('gm_hdlcoder_localdelaybalancing_sharing');
set_param('gm_hdlcoder_localdelaybalancing_sharing_vnl', 'SimulationCommand', 'update');
### Generating HDL for 'hdlcoder_localdelaybalancing_sharing/Subsystem'.
### Using the config set for model <a href="matlab:configset.showParameterGroup('hdlcoder_localdelaybalancing_sharing', { 'HDL Code Generation' } )">hdlcoder_localdelaybalancing_sharing</a> for HDL code generation parameters.
### Running HDL checks on the model 'hdlcoder_localdelaybalancing_sharing'.
### Begin compilation of the model 'hdlcoder_localdelaybalancing_sharing'...
### Applying HDL optimizations on the model 'hdlcoder_localdelaybalancing_sharing'...
### Working on... <a href="matlab:configset.internal.open('hdlcoder_localdelaybalancing_sharing', 'GenerateModel')">GenerateModel</a>
### Begin model generation.
### Model generation complete.
### Generating new validation model: <a href="matlab:open_system('hdlsrc/hdlcoder_localdelaybalancing_sharing/gm_hdlcoder_localdelaybalancing_sharing_vnl')">gm_hdlcoder_localdelaybalancing_sharing_vnl</a>.
### Validation model generation complete.
### Begin VHDL Code Generation for 'hdlcoder_localdelaybalancing_sharing'.
### MESSAGE: The design requires 2 times faster clock with respect to the base rate = 0.1.
### Begin VHDL Code Generation for 'Subsystem_tc'.
### Working on Subsystem_tc as hdlsrc/hdlcoder_localdelaybalancing_sharing/Subsystem_tc.vhd.
### Code Generation for 'Subsystem_tc' completed.
### Working on hdlcoder_localdelaybalancing_sharing/Subsystem/Subsystem as hdlsrc/hdlcoder_localdelaybalancing_sharing/Subsystem_block.vhd.
### Working on hdlcoder_localdelaybalancing_sharing/Subsystem as hdlsrc/hdlcoder_localdelaybalancing_sharing/Subsystem.vhd.
### Generating package file hdlsrc/hdlcoder_localdelaybalancing_sharing/Subsystem_pkg.vhd.
### Code Generation for 'hdlcoder_localdelaybalancing_sharing' completed.
### Creating HDL Code Generation Check Report file:///tmp/Bdoc22b_2054784_3453254/tp59df1693/hdlcoder-ex13756842/hdlsrc/hdlcoder_localdelaybalancing_sharing/Subsystem_report.html
### HDL check for 'hdlcoder_localdelaybalancing_sharing' complete with 0 errors, 0 warnings, and 2 messages.
### HDL code generation complete.

Notice that not only does sharing succeed in the inner subsystem, but local delay balancing also succeeds within this subsystem by inserting matching delays on the inputs to the adder.

open_system('gm_hdlcoder_localdelaybalancing_sharing_vnl/Subsystem/Subsystem');

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