Digital I/O with Speedgoat FPGA Board
This example shows a workflow that uses HDL Coder™ to deploy a Simulink® subsystem to a Speedgoat FPGA I/O board that resides in the target computer. A Simulink® Real-Time™ application runs on the target computer and communicates with the FPGA over the PCI bus.
In this case, the FPGA algorithm maps Simulink Real-Time generated pulse trains to I/O channels on the FPGA. Over the PCI bus, the FPGA receives pulses generated on the target computer. It then writes the signals to eight output channels. The FPGA reads eight input channels and sends them over the PCI bus to the target computer for graphical display. You accomplish loopback by wiring inputs to outputs (output channel 0 to input channel 0, output channel 1 to input channel 1, and so on).
This example uses the Speedgoat IO331. You can use any FPGA I/O module supported by Simulink Real-Time and HDL Coder that meets the speed, size, and pinout requirements of the model.
The default FPGA clock rate is 75 MHz. The Simulink Real-Time simulation is set to 1 kHz.
- Requirements and Preconditions
- Open the FPGA Domain Model
- Using the HDL Workflow Advisor
- Task 1.1. Set Target Device and Synthesis Tool
- Task 1.2. Set Target Interface
- Task 5.2. Generate Simulink Real-Time Interface
- Open the Simulink Real-Time Model
- Add the Simulink Real-Time Interface Subsystem
- Test the Model
Requirements and Preconditions
For the IO331 board, HDL Workflow Advisor requires the Xilinx® ISE toolset. To install this toolset, in the Command Window, type:
hdlsetuptoolpath('ToolName', 'Xilinx ISE', 'ToolPath', toolpath)
where toolpath is the full path to the synthesis tool executable.
For the toolset requirements of other boards, see Supported Third-Party Tools and Hardware (HDL Coder).
Open the FPGA Domain Model
Click here to open the FPGA model: dslrtSGFPGAloopback_fpga.
This model contains the algorithm (green subsystem) that will eventually run on the FPGA. It also contains some test blocks to verify, in simulation, the algorithm is working as expected before synthesizing the FPGA bitstream. Note that this model is an "FPGA domain" model, meaning the simulation sample rate is representative of the clock rate of the FPGA (75 MHz). Hence, 1 second of simulation requires 75e6 iterations of the model.
Once the algorithm is complete, use the HDL Workflow Advisor to:
- Select the FPGA I/O board
- Map the subsystem inports and outports
- Synthesize the FPGA bitstream
- Generate the Simulink Real-Time interface subsystem
Using the HDL Workflow Advisor
To invoke the HDL Workflow Advisor, right-click on the "loopback" subsystem and select HDL Code -> HDL Workflow Advisor.
Task 1.1. Set Target Device and Synthesis Tool
Select Simulink Real-Time by choosing FPGA Turnkey for Target workflow. Set the target platform to the Speedgoat IO331 and check that HDL Workflow advisor sets the synthesis tool to the Xilinx® ISE Design Suite. This setting configures the board characteristics and synthesis tool used in subsequent tasks.
When done, click Run This Task and continue with Task 1.2.
Task 1.2. Set Target Interface
Use the Target Platform Interface Table to specify and map the inports and outports. For this example,
- hwIn C0-7 are signals read from the LVCMOS I/O channels 0-7 (input channels)
- hwOut C0-7 are signals written to the LVCMOS I/O channels 8-15 (output channels)
- pciRead C0-7 are signals read from the target computer over the PCI bus (input channels)
- pciWrite C0-7 are signals written to the target computer over the PCI bus (output channels)
When done, click Run This Task and continue with Task 5.2.
Task 5.2. Generate Simulink Real-Time Interface
Right-click Task 5.2 and click Run to Selected Task. The HDL Workflow Advisor will run the tasks, synthesize the FPGA bitstream, and generate a new model which contains a Simulink Real-Time interface subsystem.
Upon completion, a newly generated model containing the Simulink Real-Time interface subsystem appears. On the surface, this subsystem looks like the FPGA subsystem. However, inside, the Simulink algorithm has been removed and replaced with blocks that the real-time application will use to communicate with the FPGA during simulation execution.
Open the Simulink Real-Time Model
Create or open a Simulink Real-Time model that will run on the target computer while the bitstream algorithm runs on the FPGA.
Click here to open the Simulink Real-Time model: dslrtSGFPGAloopback_slrt.
Add the Simulink Real-Time Interface Subsystem
From the generated model, copy the Simulink Real-Time interface subsystem and paste it in the Simulink Real-Time model. Connect inports and outports. Double-click the interface subsystem and set mask parameters as required.
Click here to open the Simulink Real-Time model with the interface subsystem included: dslrtSGFPGAloopback_slrt_wiss.
Test the Model
Build the model. Upon build completion, the Simulink Real-Time application is downloaded to the target computer and the bitstream is downloaded to the FPGA.
Run the application. The eight pulse train signals sent and received through the FPGA and the LVCMOS I/O channels are displayed on the target scope.