Main Content

HDL FIFO

Stores sequence of input samples in first in, first out (FIFO) register

  • HDL FIFO block

Libraries:
HDL Coder / HDL RAMs

Description

The HDL FIFO block stores a sequence of input samples in a first in, first out (FIFO) register. The data written first into the FIFO register comes out first. The block implementation resembles the FIFO unit in hardware platforms in terms of functionality and behavior.

The HDL FIFO block uses the Simple Dual Port RAM System block internally. You can use the HDL FIFO block to generate HDL code that maps to RAM in most FPGAs.

Limitations

  • When you build the FPGA bitstream for the HDL FIFO block, the global reset logic does not reset the FIFO register in the block. To reset the FIFO register, make sure that you implement a reset logic.

  • The HDL FIFO block does not support continuous sample time. You must specify a discrete sample time type input to the HDL FIFO block.

Ports

Input

expand all

Data input signal to the FIFO block. When you write data into the FIFO, the newest data is pushed to the end of the FIFO register. The block pushes subsequent data entries below this entry.

Data Types: single | double | half | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point
Complex Number Support: Yes

When this port receives a value of 1, the block pushes the input at the In port onto the end of the FIFO register.

Data Types: Boolean

When this port receives a value of 1, the block pops the first element off the FIFO register and holds the Out port at that value.

Data Types: Boolean

Note

If two or more of the control input ports are triggered in the same time step, the pop operation executes first, followed by the push operation.

When the reset port receives a value of 1, it resets the Empty, Full, and Num outputs of the HDL FIFO block.

Dependencies

To enable this port, select the block parameter Local reset port.

Data Types: Boolean

Output

expand all

Data output signal from the FIFO block. When you read data from the FIFO, the data that you wrote first into the FIFO register comes off the FIFO and is held at the output.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point
Complex Number Support: Yes

Control signal output from the FIFO that becomes 1 when the FIFO register is empty and does not contain data entries.

Dependencies

To enable this port, Show empty register indicator port (Empty) must be selected.

Data Types: Boolean

Control signal output from the FIFO that becomes 1 when the FIFO register is full and cannot take more data entries.

Dependencies

To enable this port, Show full register indicator port (Full) must be selected.

Data Types: Boolean

Number of data entries that are currently inside the FIFO register. Num increments by 1 for every data that you write into the FIFO. Num decrements by 1 for every data that you read from the FIFO.

Dependencies

To enable this port, Show number of entries register port (Num) must be selected.

Data Types: double

Parameters

expand all

Specify the number of entries that the FIFO register can hold. The default value for Register size is 10. The minimum value for Register size is 4.

Programmatic Use

Block parameter: fifo_size
Type: character vector
Value: An integer greater than or equal to four
Default: '10'

Specify the operation mode of the FIFO. By default, the Mode is set to Classic. You see that the block icon displays Classic FIFO. You can change the Mode to FWFT. When you change the Mode, the block icon displays FWFT FIFO. By using the FWFT mode, you can lookahead and see the first word written to the FIFO register without placing a read request. The FWFT mode is especially useful when you apply the back-pressure with AXI4-Stream interfaces.

Programmatic Use

Block parameter: mode
Type: character vector
Value: 'Classic' | 'FWFT' |
Default: 'Classic'

Specify the ratio of output sample time to input sample time. The default ratio is 1, which means that the inputs In and Push, and outputs Out and Pop, run at the same sample rate. The inputs and outputs can run at different sample times. Use a positive integer or 1/N, where N is a positive integer. For example, if you enter 1/2, the output sample time is half the input sample time, or the outputs run faster. The Full, Empty, and Num signals run at the faster rate.

Programmatic Use

Block parameter: ratio
Type: character vector
Value: An integer greater than or equal to one
Default: '1'

Specify how you want the block to respond when you write to a FIFO that is full. The default is Warning.

Programmatic Use

Block parameter: push_msg
Type: character vector
Value: 'Warning' | 'Ignore' | 'Error'
Default: 'Warning'

Specify how you want the block to respond when you read from a FIFO that is empty. The default is Warning.

Programmatic Use

Block parameter: pop_msg
Type: character vector
Value: 'Warning' | 'Ignore' | 'Error'
Default: 'Warning'

Specify whether to enable the Empty output port. This port outputs a 1 when the FIFO register is empty and 0 when the FIFO contains one or more data entries.

Programmatic Use

Block parameter: show_empty
Type: character vector
Value: 'on' | 'off'
Default: 'on'

Specify whether to enable the Full output port. This port outputs a 1 when the FIFO register is full.

Programmatic Use

Block parameter: show_full
Type: character vector
Value: 'on' | 'off'
Default: 'on'

Specify whether to enable the Num output port. This port outputs the number of data entries that are currently available in the FIFO queue.

Programmatic Use

Block parameter: show_num
Type: character vector
Value: 'on' | 'off'
Default: 'on'

Specify whether to insert an additional rst input port.

Programmatic Use

Block parameter: rst_port
Type: character vector
Value: 'on' | 'off'
Default: 'off'

Algorithms

expand all

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Version History

Introduced in R2014a

expand all