HDL Verifier™ automates the verification of HDL code on Altera® FPGA boards by enabling FPGA-in-the-loop (FIL) testing. FIL testing helps ensure that the MATLAB® algorithm or Simulink® design behaves as expected in the real world, increasing confidence in your silicon implementation. The MATLAB algorithm or Simulink model is used to drive FPGA input stimuli and to analyze the output of the FPGA. With FIL testing, you can verify your design at FPGA speeds, enabling you to run more extensive sets of test cases and perform regression tests on your design.
HDL Verifier supports FIL verification over the Gigabit Ethernet interface or over JTAG for select Altera boards with Stratix V, Stratix IV, Cyclone V, Cyclone IV, Cyclone III, Arria II, Arria V, and Arria V SoC FPGAs.
Support Package Installer installs this support package. To start the installer, go to the MATLAB toolstrip and click Add-Ons > Get Hardware Support Packages. For more information, read the documentation.
One of the following Altera® kits or boards: