Set up an FPGA-in-the-Loop (FIL) application using HDL Verifier™. The application uses Simulink® and an FPGA development board to verify the HDL implementation of a
Verify generated HDL code using HDL Cosimulation and FPGA-in-the-Loop as steps in the HDL code generation workflow for MATLAB to HDL.
Uses FPGA-in-the-Loop (FIL) simulation to accelerate a video processing simulation with Simulink® by adding an FPGA. The process shown analyzes a simple system that sharpens an RGB video
Use HDL Verifier™ in conjunction with ModelSim® to verify HDL code for a fixed-point Viterbi decoder.
Run Incisive® HDL Simulator in batch mode to test an HDL component with a MATLAB® test bench. In this example, we compile an HDL low-pass filter - designed and generated with the Filter Design
Use a MATLAB System object and a FPGA to verify a register transfer level (RTL) design of a Fast Fourier Transform (FFT) of size 8 written in Verilog. The FFT is commonly used in digital signal
Achieve complete code coverage of an HDL cruise controller design using Simulink® and ModelSim®.
Verify a digital up-converter design generated with Filter Design HDL Coder™ using FPGA-in-the-Loop simulation.
Guides you through the basic steps for setting up an HDL Verifier™ application using the Cosimulation Wizard.
Verification of a Manchester encoder using Simulink and HDL Verifier. Manchester encoding is a simple modulation scheme that converts baseband digital data to an encoded waveform with no
The Manchester Receiver example shows how to use the HDL Verifier™ to design, test, and verify a VHDL Manchester Receiver model with clock recovery capabilities.
Uses FPGA-in-the-Loop (FIL) simulation to accelerate part of a communications system. The application uses the Viterbi Algorithm to decode a convolutional encoded random stream that is
Illustrates the relationship of Simulink® sample times to HDL clocks and resets by using the HDL Verifier™ to cosimulate a simple synchronous Verilog parity check module. The example also
Illustrates verification of a receiver of Manchester encoded data. Manchester encoding is a simple modulation scheme that converts baseband digital data to an encoded waveform with no DC
The full workflow of how to generate a SystemVerilog DPI component for a FIFO buffer interface meant to be integrated with a UART receiver.The interface is written in MATLAB, and exported to
Verification of a Manchester enocder using mixed HDL languages, VHDL and Verilog. Manchester encoding is a simple modulation scheme which converts baseband digital data into an encoded
Illustrates the validation of a VHDL implementation of a 6-order scrambler. A scrambler is used in communication systems to randomize transitions in the transmitted signal by shuffling
This model simulates a digital receiver of Manchester encoded data. Manchester encoding is a simple modulation scheme that converts baseband digital data to an encoded waveform with no DC
Uses HDL cosimulation and FPGA-in-the-Loop (FIL) simulation to verify an HDL design comprising generated and legacy HDL code. The term "legacy" is used here to indicate code that may have
Illustrates the various Timescale settings within the HDL Cosimulation block and explains how these affect the timing relationship of Simulink® and the HDL simulator. We use a simple
Generate a SystemVerilog DPI component for a programmable square-wave generator written in MATLAB, and export it to an HDL simulator.
Achieve complete code coverage of an HDL cruise controller design using Simulink® and Cadence® Incisive®.
Use MATLAB® System objects and Mentor Graphics® ModelSim® to cosimulate a Viterbi decoder implemented in VHDL.
Use Simulink® Design Verifier™ functions to log input signals, create a harness model, generate test cases for missing coverage, merge harness models, and execute test cases.
Use Simulink® Design Verifier™ functions to replace unsupported blocks and to how customize test vector generation for specific requirements.
Verify the seat belt reminder design model referenced in the top block above.
Verify the seat belt reminder design model referenced in the top block above.
How Simulink® Design Verifier™ can extend test cases with additional time steps to efficiently generate complete test suites.
Use Simulink Design Verifier to extend a test suite such that it satisfies missing model coverage. In this manner, you can reuse test data as you modify a model and limit test generation only to
How Simulink® Design Verifier™ can target its analysis to a single subsystem within a continuous-time closed-loop simulation and generate test cases for missing coverage in that
Find a property violation using Simulink Design Verifier property proving analysis.
Perform a Simulink Design Verifier property proof using a Proof Assumption block.
Verify safety properties in a thrust reverser design model.
Model temporal system requirements for property proving and test case generation using Simulink® Design Verifier™ Temporal Operator blocks.
Model temporal system requirements in a power window controller model for property proving and test case generation using Simulink® Design Verifier™ Temporal Operator blocks.
Use input port minimum and maximum values as analysis constraints by Simulink Design Verifier during both test generation and property proving.
Use Simulink® Design Verifier™ command-line functions to generate test data that incorporates different parameter values.
Prove properties in a fixed-point cruise control algorithm.
Generate test cases that satisfy Decision, Condition, and MCDC coverage.
Generate test cases that achieve complete model coverage for a debouncer.
Generate test cases based on model hierarchy. Copyright 2015 The MathWorks, Inc.
Perform code generation verification for a model. Copyright 2015 The MathWorks, Inc.
Report test results for a baseline test. Copyright 2015 The MathWorks, Inc.
Increase coverage of a test case by generating tests using Simulink® Design Verifier™. Copyright 2016 The MathWorks, Inc.
Verify a model against a baseline using a parameter override and the Test Manager. Copyright 2015 The MathWorks, Inc.
Change test harness settings for different verification objectives.
Demonstrates how to test a transmission shift logic controller using test sequences and test assessments.
Test and optimize a physical system using a test sequence, test harness, and the test manager. Copyright 2015 The MathWorks, Inc.
Demonstrates cloning an existing test harness and exporting the cloned harness to a separate model. This can be useful if you want to create a copy of a test harness as a separate model, but
Synchronize and rebuild a test harness from the main model.
Test a transmission controller using a test harness and test sequence.
Reuse test assessments contained in a test sequence block using a linked block from a library.
Use waveforms to test a component under test. Copyright 2015 The MathWorks, Inc.
Verify a reusable subsystem in a library and in a larger system. Copyright 2016 The MathWorks, Inc.
Create a test harness to schedule function calls for export function models.
Perform real-time testing on a target computer and verify system behavior against requirements. Copyright 2016 The MathWorks, Inc.
Delete test harnesses programmatically. Deleting with % the programmatic interface can be useful when your model has multiple test harnesses at different hierarchy levels. This example
Import a standalone test model to create a test harness in Simulink Test.
Requirements Management Interface (RMI) provides tools for creating and reviewing links between Simulink objects and requirements documents. This example illustrates linking model
Use Simulink® Verification and Validation™ model coverage filters to exclude model items from coverage recording and justify missing coverage in reports.
Use Simulink® Verification and Validation™ component verification functions to log input signals, create a harness model, and execute test cases.
Traceability management support in the MATLAB Editor is an extension of the Simulink-based Requirements Management Interface to allow associations between MATLAB code lines and
Create and manage traceability associations for MATLAB® code lines in MATLAB files, using the Requirements Management Interface (RMI). This is similar to creating traceability
You can use Simulink to model your design requirements. For example, you can use verification blocks to specify desired system properties and model the design requirements. The
The Requirements Management Interface (RMI) provides tools for creating and reviewing links between Simulink objects and requirements documents. This example illustrates linking
Use the dialog box for coverage settings to enable coverage for a Simulink® model and adjust the type of information that is reported.
Illustrates the use of the Coverage Results Explorer to simplify the generation of cumulative coverage data and reports spanning a set of multiple coverage runs.
Creates three test cases for an adjustable rate limiter and analyzes the resulting model coverage using the command-line API of the Model Coverage tool.
The requirements report is a feature in RMI that scans the Simulink model for links to external requirements documents and generates a report. When documents are available for reading
How coverage information for a model is bundled in the cvdata object and how utility commands can extract information from it for an individual subsystem, block, or Stateflow® object.
Configure an S-Function generated with the Legacy Code Tool to be compatible with coverage. The model coverage tool supports S-Functions that are:
Historically, when linking requirements documents to Simulink objects, link information is stored with the model file. Model files are therefore modified every time you add, modify, or
Use the overloaded operators +, *, and - to combine coverage results into a union, intersection, or set difference of results.
The application of coverage analysis to a simple design problem and compares the coverage requirements for different metrics.
how to create and view cumulative coverage results for a model with a reusable subsystem.
Simulate this model to collect and report Saturate on integer overflow coverage.
Illustrates the association of Microsoft® Word requirements for a fault-tolerant fuel control system with its model implemented in Simulink® and Stateflow®.
Model explains how Model Coverage relates to MATLAB code inside a MATLAB Function Block.
Illustrates the association of HTML requirements for a fault-tolerant fuel control system with its model implemented in Simulink® and Stateflow®.